From patchwork Wed Mar 14 17:52:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jackie Li X-Patchwork-Id: 10283149 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3D13460621 for ; Wed, 14 Mar 2018 17:54:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2EDED28538 for ; Wed, 14 Mar 2018 17:54:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 235D528543; Wed, 14 Mar 2018 17:54:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7788E28538 for ; Wed, 14 Mar 2018 17:54:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D90C16E6AE; Wed, 14 Mar 2018 17:54:06 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A29426E6AE for ; Wed, 14 Mar 2018 17:54:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Mar 2018 10:54:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,306,1517904000"; d="scan'208";a="33857315" Received: from yli84-z170x-ud5.fm.intel.com ([10.19.83.14]) by FMSMGA003.fm.intel.com with ESMTP; 14 Mar 2018 10:54:04 -0700 From: Jackie Li To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Mar 2018 10:52:05 -0700 Message-Id: <1521049925-31225-1-git-send-email-yaodong.li@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH] drm/i915: Use correct reST syntax for WOPCM and GuC kernel-doc diagrams X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GuC Address Space and WOPCM Layout diagrams won't be generated correctly by sphinx build if not using proper reST syntax. This patch uses reST literal blocks to make sure GuC Address Space and WOPCM Layout diagrams to be generated correctly. Signed-off-by: Jackie Li Cc: Michal Wajdeczko Cc: Sagar Arun Kamble Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_guc.c | 46 ++++++++++++++++++++------------------ drivers/gpu/drm/i915/intel_wopcm.c | 40 +++++++++++++++++---------------- 2 files changed, 45 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 3eb516e..61d00f8 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -497,28 +497,30 @@ int intel_guc_resume(struct intel_guc *guc) * * The layout of GuC address space is shown as below: * - * +==============> +====================+ <== GUC_GGTT_TOP - * ^ | | - * | | | - * | | DRAM | - * | | Memory | - * | | | - * GuC | | - * Address +========> +====================+ <== WOPCM Top - * Space ^ | HW contexts RSVD | - * | | | WOPCM | - * | | +==> +--------------------+ <== GuC WOPCM Top - * | GuC ^ | | - * | GGTT | | | - * | Pin GuC | GuC | - * | Bias WOPCM | WOPCM | - * | | Size | | - * | | | | | - * v v v | | - * +=====+=====+==> +====================+ <== GuC WOPCM Base - * | Non-GuC WOPCM | - * | (HuC/Reserved) | - * +====================+ <== WOPCM Base + * :: + * + * +==============> +====================+ <== GUC_GGTT_TOP + * ^ | | + * | | | + * | | DRAM | + * | | Memory | + * | | | + * GuC | | + * Address +========> +====================+ <== WOPCM Top + * Space ^ | HW contexts RSVD | + * | | | WOPCM | + * | | +==> +--------------------+ <== GuC WOPCM Top + * | GuC ^ | | + * | GGTT | | | + * | Pin GuC | GuC | + * | Bias WOPCM | WOPCM | + * | | Size | | + * | | | | | + * v v v | | + * +=====+=====+==> +====================+ <== GuC WOPCM Base + * | Non-GuC WOPCM | + * | (HuC/Reserved) | + * +====================+ <== WOPCM Base * * The lower part [0, GuC ggtt_pin_bias) is mapped to WOPCM which consists of * GuC WOPCM and WOPCM reserved for other usage (e.g.RC6 context). The value of diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 4117886..030debd 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -14,25 +14,27 @@ * offset registers whose are calculated are determined by size of HuC/GuC * firmware size and set of hw requirements/restrictions as shown below: * - * +=========> +====================+ <== WOPCM Top - * ^ | HW contexts RSVD | - * | +===> +====================+ <== GuC WOPCM Top - * | ^ | | - * | | | | - * | | | | - * | GuC | | - * | WOPCM | | - * | Size +--------------------+ - * WOPCM | | GuC FW RSVD | - * | | +--------------------+ - * | | | GuC Stack RSVD | - * | | +------------------- + - * | v | GuC WOPCM RSVD | - * | +===> +====================+ <== GuC WOPCM base - * | | WOPCM RSVD | - * | +------------------- + <== HuC Firmware Top - * v | HuC FW | - * +=========> +====================+ <== WOPCM Base + * :: + * + * +=========> +====================+ <== WOPCM Top + * ^ | HW contexts RSVD | + * | +===> +====================+ <== GuC WOPCM Top + * | ^ | | + * | | | | + * | | | | + * | GuC | | + * | WOPCM | | + * | Size +--------------------+ + * WOPCM | | GuC FW RSVD | + * | | +--------------------+ + * | | | GuC Stack RSVD | + * | | +------------------- + + * | v | GuC WOPCM RSVD | + * | +===> +====================+ <== GuC WOPCM base + * | | WOPCM RSVD | + * | +------------------- + <== HuC Firmware Top + * v | HuC FW | + * +=========> +====================+ <== WOPCM Base * * GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top. * The top part of the WOPCM is reserved for hardware contexts (e.g. RC6