From patchwork Mon Mar 19 12:37:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lis, Tomasz" X-Patchwork-Id: 10292273 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A3077600F6 for ; Mon, 19 Mar 2018 12:37:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9164328FD3 for ; Mon, 19 Mar 2018 12:37:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 84BC22905A; Mon, 19 Mar 2018 12:37:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 19F1028FD3 for ; Mon, 19 Mar 2018 12:37:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D9E96E257; Mon, 19 Mar 2018 12:37:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id C36CB6E184 for ; Mon, 19 Mar 2018 12:37:40 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2018 05:37:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,330,1517904000"; d="scan'208";a="29252599" Received: from gklab-178-192.igk.intel.com (HELO szara.igk.intel.com) ([172.28.178.192]) by fmsmga002.fm.intel.com with ESMTP; 19 Mar 2018 05:37:39 -0700 From: Tomasz Lis To: intel-gfx@lists.freedesktop.org Date: Mon, 19 Mar 2018 13:37:35 +0100 Message-Id: <1521463055-5325-2-git-send-email-tomasz.lis@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521463055-5325-1-git-send-email-tomasz.lis@intel.com> References: <1521463055-5325-1-git-send-email-tomasz.lis@intel.com> Subject: [Intel-gfx] [RFC v1] drm/i915: Add Exec param to control data port coherency. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bartosz.dunajski@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The patch adds a parameter to control the data port coherency functionality on a per-exec call basis. When data port coherency flag value is different than what it was in previous call for the context, a command to switch data port coherency state is added before the buffer to be executed. Bspec: 11419 --- drivers/gpu/drm/i915/i915_drv.c | 3 ++ drivers/gpu/drm/i915/i915_gem_context.h | 1 + drivers/gpu/drm/i915/i915_gem_execbuffer.c | 17 ++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 53 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.h | 3 ++ include/uapi/drm/i915_drm.h | 12 ++++++- 6 files changed, 88 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 3df5193..fcb3547 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -436,6 +436,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, case I915_PARAM_CS_TIMESTAMP_FREQUENCY: value = 1000 * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz; break; + case I915_PARAM_HAS_EXEC_DATA_PORT_COHERENCY: + value = (INTEL_GEN(dev_priv) >= 9); + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 7854262..00aa309 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -118,6 +118,7 @@ struct i915_gem_context { #define CONTEXT_BANNABLE 3 #define CONTEXT_BANNED 4 #define CONTEXT_FORCE_SINGLE_SUBMISSION 5 +#define CONTEXT_DATA_PORT_COHERENT 6 /** * @hw_id: - unique identifier for the context diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 8c170db..f848f14 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -2245,6 +2245,18 @@ i915_gem_do_execbuffer(struct drm_device *dev, eb.batch_flags |= I915_DISPATCH_RS; } + if (args->flags & I915_EXEC_DATA_PORT_COHERENT) { + if (INTEL_GEN(eb.i915) < 9) { + DRM_DEBUG("Data Port Coherency is only allowed for Gen9 and above\n"); + return -EINVAL; + } + if (eb.engine->class != RENDER_CLASS) { + DRM_DEBUG("Data Port Coherency is not available on %s\n", + eb.engine->name); + return -EINVAL; + } + } + if (args->flags & I915_EXEC_FENCE_IN) { in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2)); if (!in_fence) @@ -2371,6 +2383,11 @@ i915_gem_do_execbuffer(struct drm_device *dev, goto err_batch_unpin; } + /* Emit the switch of data port coherency state if needed */ + err = intel_lr_context_modify_data_port_coherency(eb.request, + (args->flags & I915_EXEC_DATA_PORT_COHERENT) != 0); + GEM_WARN_ON(err); + if (in_fence) { err = i915_request_await_dma_fence(eb.request, in_fence); if (err < 0) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 53f1c00..b847798 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -254,6 +254,59 @@ intel_lr_context_descriptor_update(struct i915_gem_context *ctx, ce->lrc_desc = desc; } +static int emit_set_data_port_coherency(struct i915_request *req, bool enable) +{ + u32 *cs; + i915_reg_t reg; + + GEM_BUG_ON(req->engine->class != RENDER_CLASS); + GEM_BUG_ON(INTEL_GEN(req->i915) < 9); + + cs = intel_ring_begin(req, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + if (INTEL_GEN(req->i915) >= 10) + reg = CNL_HDC_CHICKEN0; + else + reg = HDC_CHICKEN0; + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(reg); + /* Enabling coherency means disabling the bit which forces it off */ + if (enable) + *cs++ = _MASKED_BIT_DISABLE(HDC_FORCE_NON_COHERENT); + else + *cs++ = _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT); + *cs++ = MI_NOOP; + + intel_ring_advance(req, cs); + + return 0; +} + +int +intel_lr_context_modify_data_port_coherency(struct i915_request *req, + bool enable) +{ + struct i915_gem_context *ctx = req->ctx; + int ret; + + if (test_bit(CONTEXT_DATA_PORT_COHERENT, &ctx->flags) == enable) + return 0; + + ret = emit_set_data_port_coherency(req, enable); + + if (!ret) { + if (enable) + __set_bit(CONTEXT_DATA_PORT_COHERENT, &ctx->flags); + else + __clear_bit(CONTEXT_DATA_PORT_COHERENT, &ctx->flags); + } + + return ret; +} + static struct i915_priolist * lookup_priolist(struct intel_engine_cs *engine, struct i915_priotree *pt, diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 59d7b86..c46b239 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -111,4 +111,7 @@ intel_lr_context_descriptor(struct i915_gem_context *ctx, return ctx->engine[engine->id].lrc_desc; } +int intel_lr_context_modify_data_port_coherency(struct i915_request *req, + bool enable); + #endif /* _INTEL_LRC_H_ */ diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 7f5634c..a5fed1f 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -529,6 +529,11 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to switch + * Data Cache access into Data Port Coherency mode. + */ +#define I915_PARAM_HAS_EXEC_DATA_PORT_COHERENCY 52 + typedef struct drm_i915_getparam { __s32 param; /* @@ -1048,7 +1053,12 @@ struct drm_i915_gem_execbuffer2 { */ #define I915_EXEC_FENCE_ARRAY (1<<19) -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1)) +/* Data Port Coherency capability will be switched before an exec call + * which has this flag different than previous call for the context. + */ +#define I915_EXEC_DATA_PORT_COHERENT (1<<20) + +#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_DATA_PORT_COHERENT<<1)) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \