From patchwork Mon Apr 2 08:37:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Xiong Y" X-Patchwork-Id: 10319479 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8002F60467 for ; Mon, 2 Apr 2018 08:38:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71E1D28AFB for ; Mon, 2 Apr 2018 08:38:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6480F28B12; Mon, 2 Apr 2018 08:38:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B2AF228AFB for ; Mon, 2 Apr 2018 08:38:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 758406E07F; Mon, 2 Apr 2018 08:38:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 308D86E07F; Mon, 2 Apr 2018 08:38:36 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Apr 2018 01:38:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,394,1517904000"; d="scan'208";a="40025599" Received: from test-optiplex-7040.bj.intel.com ([10.238.154.174]) by orsmga003.jf.intel.com with ESMTP; 02 Apr 2018 01:38:34 -0700 From: Xiong Zhang To: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Mon, 2 Apr 2018 16:37:55 +0800 Message-Id: <1522658275-3262-1-git-send-email-xiong.y.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <152231666514.4289.6376474309139408597@jlahtine-desk.ger.corp.intel.com> References: <152231666514.4289.6376474309139408597@jlahtine-desk.ger.corp.intel.com> Subject: [Intel-gfx] [PATCH] drm/i915: Move vgpu balloon info into i915_virtual_gpu struct X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP vgpu ballon info consists of four drm_mm_node which is used to reserve ggtt space, then linux guest won't use these reserved ggtt space. Each vgpu has its own ballon info, so move ballon info into i915_virtual_gpu structure. Signed-off-by: Xiong Zhang Acked-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++++++ drivers/gpu/drm/i915/i915_vgpu.c | 47 ++++++++++++++++++++-------------------- 2 files changed, 37 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 800230b..2adc73d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1301,6 +1301,20 @@ struct i915_workarounds { struct i915_virtual_gpu { bool active; u32 caps; + + struct balloon_info { + /* + * There are up to 2 regions per mappable/unmappable graphic + * memory that might be ballooned. Here, index 0/1 is for + * mappable graphic memory, 2/3 for unmappable graphic memory. + */ +#define VGPU_MAPPABLE_BALLOON_LOW 0 +#define VGPU_MAPPABLE_BALLOON_HIGH 1 +#define VGPU_UNMAPPABLE_BALLOON_LOW 2 +#define VGPU_UNMAPPABLE_BALLOON_HIGH 3 +#define VGPU_MAX_BALLOON_NUM 4 + struct drm_mm_node space[VGPU_MAX_BALLOON_NUM]; + } bl_info; }; /* used in computing the new watermarks state */ diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index 7545686..79d3df4 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -86,17 +86,6 @@ bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv) return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT; } -struct _balloon_info_ { - /* - * There are up to 2 regions per mappable/unmappable graphic - * memory that might be ballooned. Here, index 0/1 is for mappable - * graphic memory, 2/3 for unmappable graphic memory. - */ - struct drm_mm_node space[4]; -}; - -static struct _balloon_info_ bl_info; - static void vgt_deballoon_space(struct i915_ggtt *ggtt, struct drm_mm_node *node) { @@ -128,8 +117,9 @@ void intel_vgt_deballoon(struct drm_i915_private *dev_priv) DRM_DEBUG("VGT deballoon.\n"); - for (i = 0; i < 4; i++) - vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]); + for (i = 0; i < VGPU_MAX_BALLOON_NUM; i++) + vgt_deballoon_space(&dev_priv->ggtt, + &dev_priv->vgpu.bl_info.space[i]); } static int vgt_balloon_space(struct i915_ggtt *ggtt, @@ -200,6 +190,7 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt, int intel_vgt_balloon(struct drm_i915_private *dev_priv) { struct i915_ggtt *ggtt = &dev_priv->ggtt; + struct balloon_info *bl_info; unsigned long ggtt_end = ggtt->base.total; unsigned long mappable_base, mappable_size, mappable_end; @@ -230,34 +221,39 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) return -EINVAL; } + bl_info = &dev_priv->vgpu.bl_info; /* Unmappable graphic memory ballooning */ if (unmappable_base > ggtt->mappable_end) { - ret = vgt_balloon_space(ggtt, &bl_info.space[2], - ggtt->mappable_end, unmappable_base); + ret = vgt_balloon_space(ggtt, + &bl_info->space[VGPU_UNMAPPABLE_BALLOON_LOW], + ggtt->mappable_end, unmappable_base); if (ret) goto err; } if (unmappable_end < ggtt_end) { - ret = vgt_balloon_space(ggtt, &bl_info.space[3], - unmappable_end, ggtt_end); + ret = vgt_balloon_space(ggtt, + &bl_info->space[VGPU_UNMAPPABLE_BALLOON_HIGH], + unmappable_end, ggtt_end); if (ret) goto err_upon_mappable; } /* Mappable graphic memory ballooning */ if (mappable_base) { - ret = vgt_balloon_space(ggtt, &bl_info.space[0], - 0, mappable_base); + ret = vgt_balloon_space(ggtt, + &bl_info->space[VGPU_MAPPABLE_BALLOON_LOW], + 0, mappable_base); if (ret) goto err_upon_unmappable; } if (mappable_end < ggtt->mappable_end) { - ret = vgt_balloon_space(ggtt, &bl_info.space[1], - mappable_end, ggtt->mappable_end); + ret = vgt_balloon_space(ggtt, + &bl_info->space[VGPU_MAPPABLE_BALLOON_HIGH], + mappable_end, ggtt->mappable_end); if (ret) goto err_below_mappable; @@ -267,11 +263,14 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) return 0; err_below_mappable: - vgt_deballoon_space(ggtt, &bl_info.space[0]); + vgt_deballoon_space(ggtt, + &bl_info->space[VGPU_MAPPABLE_BALLOON_LOW]); err_upon_unmappable: - vgt_deballoon_space(ggtt, &bl_info.space[3]); + vgt_deballoon_space(ggtt, + &bl_info->space[VGPU_UNMAPPABLE_BALLOON_HIGH]); err_upon_mappable: - vgt_deballoon_space(ggtt, &bl_info.space[2]); + vgt_deballoon_space(ggtt, + &bl_info->space[VGPU_UNMAPPABLE_BALLOON_LOW]); err: DRM_ERROR("VGT balloon fail\n"); return ret;