From patchwork Mon Apr 2 09:51:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Srinivas X-Patchwork-Id: 10319535 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EFCAF602C8 for ; Mon, 2 Apr 2018 09:55:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAD9928B0A for ; Mon, 2 Apr 2018 09:55:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CFAAD28BCD; Mon, 2 Apr 2018 09:55:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5483E28B0A for ; Mon, 2 Apr 2018 09:55:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D2AA6E068; Mon, 2 Apr 2018 09:55:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id CAA8B6E178 for ; Mon, 2 Apr 2018 09:55:27 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Apr 2018 02:55:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,395,1517904000"; d="scan'208";a="28867776" Received: from vsrini4-ubuntu.iind.intel.com ([10.223.161.6]) by fmsmga007.fm.intel.com with ESMTP; 02 Apr 2018 02:55:26 -0700 From: Vidya Srinivas To: intel-gfx@lists.freedesktop.org Date: Mon, 2 Apr 2018 15:21:55 +0530 Message-Id: <1522662715-13640-19-git-send-email-vidya.srinivas@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522662715-13640-1-git-send-email-vidya.srinivas@intel.com> References: <1522662715-13640-1-git-send-email-vidya.srinivas@intel.com> Subject: [Intel-gfx] [PATCH v19 18/18] drm/i915: Set src size restrictions for NV12 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vidya Srinivas , maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP As per display WA 1106, to avoid corruption issues NV12 plane height needs to be multiplier of 4 We expect the src dimensions to be multiplier of 4 We fail the case where src width or height is not multiple of 4 for NV12. We also set the scaler destination height and width to be multiple of 4. Without this, pipe fifo underruns were seen on APL and KBL. We also skip src trunction/adjustments for NV12 case and handle the sizes directly in skl_update_plane Credits-to: Maarten Lankhorst Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_sprite.c | 19 ++++++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9c58da0..a1f718d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -159,6 +159,8 @@ #define INTEL_I2C_BUS_DVO 1 #define INTEL_I2C_BUS_SDVO 2 +#define MULT4(x) ((x + 3) & ~0x03) + /* these are outputs from the chip - integrated only external chips are via DVO or SDVO output */ enum intel_output_type { diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index d5dad44..b2292dd 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -255,6 +255,12 @@ skl_update_plane(struct intel_plane *plane, uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; unsigned long irqflags; + if (fb->format->format == DRM_FORMAT_NV12 && + ((src_h % 4) != 0 || (src_w % 4) != 0)) { + DRM_DEBUG_KMS("NV12: src dimensions not valid\n"); + return; + } + /* Sizes are 0 based */ src_w--; src_h--; @@ -292,9 +298,12 @@ skl_update_plane(struct intel_plane *plane, PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode); I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); - I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), - ((crtc_w + 1) << 16)|(crtc_h + 1)); - + if (fb->format->format == DRM_FORMAT_NV12) + I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), + (MULT4(crtc_w) << 16) | MULT4(crtc_h)); + else + I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), + ((crtc_w + 1) << 16)|(crtc_h + 1)); I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); } else { I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); @@ -969,6 +978,9 @@ intel_check_sprite_plane(struct intel_plane *plane, return -EINVAL; } + if (fb->format->format == DRM_FORMAT_NV12) + goto check_plane_surface; + /* setup can_scale, min_scale, max_scale */ if (INTEL_GEN(dev_priv) >= 9) { if (state->base.fb) @@ -1112,6 +1124,7 @@ intel_check_sprite_plane(struct intel_plane *plane, dst->y1 = crtc_y; dst->y2 = crtc_y + crtc_h; +check_plane_surface: if (INTEL_GEN(dev_priv) >= 9) { ret = skl_check_plane_surface(crtc_state, state); if (ret)