From patchwork Tue Apr 3 10:52:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kevin.rogovin@intel.com X-Patchwork-Id: 10320951 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4B46A60318 for ; Tue, 3 Apr 2018 10:52:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C4CE204FB for ; Tue, 3 Apr 2018 10:52:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2080F223B2; Tue, 3 Apr 2018 10:52:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CA5FC204FB for ; Tue, 3 Apr 2018 10:52:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 107376E38F; Tue, 3 Apr 2018 10:52:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F80D6E38F for ; Tue, 3 Apr 2018 10:52:42 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Apr 2018 03:52:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,400,1517904000"; d="scan'208";a="43601311" Received: from rdhanapx-mobl3.gar.corp.intel.com (HELO LittleBigTrouble.ger.corp.intel.com) ([10.252.52.1]) by fmsmga001.fm.intel.com with ESMTP; 03 Apr 2018 03:52:40 -0700 From: kevin.rogovin@intel.com To: intel-gfx@lists.freedesktop.org, tvrtko.ursulin@linux.intel.com, abdiel.janulgue@linux.intel.com, joonas.lahtinen@linux.intel.com, chris@chris-wilson.co.uk Date: Tue, 3 Apr 2018 13:52:27 +0300 Message-Id: <1522752747-7836-6-git-send-email-kevin.rogovin@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522752747-7836-1-git-send-email-kevin.rogovin@intel.com> References: <1522752747-7836-1-git-send-email-kevin.rogovin@intel.com> Subject: [Intel-gfx] [PATCH v4 5/5] i915: add documentation to intel_engine_cs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Rogovin MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Kevin Rogovin Add documentation to a number of the function pointer fields of intel_engine_cs. Signed-off-by: Kevin Rogovin --- drivers/gpu/drm/i915/intel_ringbuffer.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 1f50727a5ddb..eafd1690acde 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -426,23 +426,52 @@ struct intel_engine_cs { void (*set_default_submission)(struct intel_engine_cs *engine); + /* In addition to pinning the context, returns the intel_ringbuffer + * to which to write commands. + */ struct intel_ring *(*context_pin)(struct intel_engine_cs *engine, struct i915_gem_context *ctx); void (*context_unpin)(struct intel_engine_cs *engine, struct i915_gem_context *ctx); + + /* Request room on the ringbuffer of a request in order to write + * commands for a request; In addition, if necessary, add commands + * to the buffer so that the i915_gem_context of the request + * is the one active for the commands. + */ int (*request_alloc)(struct i915_request *rq); + + /* Called only once (and only if non-NULL) for an engine; used to + * initialize the global driver default context. + */ int (*init_context)(struct i915_request *rq); + /* Add a GPU command to cache invalidate with EMIT_INVALIDATE, + * to pipeline flush with EMIT_FLUSH or to do both with EMIT_BARRIER; + * the GPU command is added to the buffer holding the commands of + * the request (i.e. calling intel_ring_begin() on + * i915_request::ring). + */ int (*emit_flush)(struct i915_request *request, u32 mode); #define EMIT_INVALIDATE BIT(0) #define EMIT_FLUSH BIT(1) #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH) + /* Add a batchbuffer start command; the GPU command is added to + * the buffer holding the commands of the request (i.e. calling + * intel_ring_begin() on i915_request::ring). + */ int (*emit_bb_start)(struct i915_request *rq, u64 offset, u32 length, unsigned int dispatch_flags); #define I915_DISPATCH_SECURE BIT(0) #define I915_DISPATCH_PINNED BIT(1) #define I915_DISPATCH_RS BIT(2) + /* Add a memory write command that writes the global sequence number + * (i915_request::global_seqno) and also add an interrupt command; + * the GPU command is added to the buffer holding the commands of + * the request (i.e. calling intel_ring_begin() on + * i915_request::ring). + */ void (*emit_breadcrumb)(struct i915_request *rq, u32 *cs); int emit_breadcrumb_sz;