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[10/22] drm/i915/icl: Wa_1406680159 and Wa_2201832410

Message ID 1523635265-9287-10-git-send-email-oscar.mateo@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

oscar.mateo@intel.com April 13, 2018, 4 p.m. UTC 
Disable GWL clock gating to prevent two different issues that
might cause hangs.

Please notice that one of the issues is pre-production only.

v2: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 76059ed..57a69aa 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -751,6 +751,12 @@  static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
 			    MSCUNIT_CLKGATE_DIS));
+
+	/* Wa_1406680159:icl */
+	/* Wa_2201832410:icl (pre-prod, only until C0) */
+	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+		    GWUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)