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[21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

Message ID 1523635265-9287-21-git-send-email-oscar.mateo@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

oscar.mateo@intel.com April 13, 2018, 4:01 p.m. UTC 
Required for TR-TT (Tiled Resource Translation Table) support.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
 2 files changed, 11 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 127d2a3..d008a70 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8255,6 +8255,9 @@  enum {
 #define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
 
+#define TR_VA_TTL3_PTR_DW0		_MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1		_MMIO(0x4DE4)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 8a76bc4..b52ac41 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -973,6 +973,14 @@  static int icl_whitelist_workarounds_apply(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
+	/* WaAllowUmdWriteTRTTRootTable:icl */
+	ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW0);
+	if (ret)
+		return ret;
+	ret = wa_ring_whitelist_reg(engine, TR_VA_TTL3_PTR_DW1);
+	if (ret)
+		return ret;
+
 	return 0;
 }