diff mbox

[v3,2/3] drm/i915/icl: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads

Message ID 1526681122-22587-1-git-send-email-yunwei.zhang@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Yunwei Zhang May 18, 2018, 10:05 p.m. UTC 
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Icelake as
well.

References: HSD#1405586840, BSID#0575

v2:
 - GEN11 mask is different from its predecessors. (Oscar)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Yunwei Zhang <yunwei.zhang@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c   | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 +++-
 2 files changed, 6 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 832419e..9b13ee3 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -829,6 +829,9 @@  u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) == 10)
 		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
 				  GEN8_MCR_SUBSLICE(subslice);
+	else if (INTEL_GEN(dev_priv) >= 11)
+		mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
+				  GEN11_MCR_SUBSLICE(subslice);
 	else
 		mcr_s_ss_select = 0;
 
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 497bf75..2deec58 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -686,7 +686,7 @@  static void wa_init_mcr(struct drm_i915_private *dev_priv)
 		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
 					  GEN8_MCR_SUBSLICE_MASK;
 	/*
-	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
 	 * Before any MMIO read into slice/subslice specific registers, MCR
 	 * packet control register needs to be programmed to point to any
 	 * enabled s/ss pair. Otherwise, incorrect values will be returned.
@@ -723,6 +723,8 @@  static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 
 static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
+	wa_init_mcr(dev_priv);
+
 	/* This is not an Wa. Enable for better image quality */
 	I915_WRITE(_3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));