From patchwork Wed Jun 13 18:41:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Kumar, Abhay" X-Patchwork-Id: 10462831 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4D642603B4 for ; Wed, 13 Jun 2018 18:43:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3E1C228A20 for ; Wed, 13 Jun 2018 18:43:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 31E3A290C3; Wed, 13 Jun 2018 18:43:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C2F9D290C2 for ; Wed, 13 Jun 2018 18:43:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 842BE6E19B; Wed, 13 Jun 2018 18:43:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id D75096E17F for ; Wed, 13 Jun 2018 18:43:42 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2018 11:43:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,220,1526367600"; d="scan'208";a="47516781" Received: from abhaykum-lin.sc.intel.com ([10.3.62.173]) by fmsmga008.fm.intel.com with ESMTP; 13 Jun 2018 11:43:40 -0700 From: Abhay Kumar To: intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com Date: Wed, 13 Jun 2018 11:41:56 -0700 Message-Id: <1528915317-14156-4-git-send-email-abhay.kumar@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528915317-14156-1-git-send-email-abhay.kumar@intel.com> References: <1528915317-14156-1-git-send-email-abhay.kumar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 3/4] drm/i915: Lock gmbus/aux mutexes while changing cdclk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä gmbus/aux may be clocked by cdclk, thus we should make sure no transfers are ongoing while the cdclk frequency is being changed. We do that by simply grabbing all the gmbus/aux mutexes. No one else should be holding any more than one of those at a time so the lock ordering here shouldn't matter. An alternative apporach would be the introduction of a cdclk rwsem. Cdclk reprogramming would take the write lock, all users of cdclk would take the read lock. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/intel_cdclk.c | 25 +++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_i2c.c | 1 - 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 4cdd70de5ed0..2a30369b9df9 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -899,6 +899,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, mutex_init(&dev_priv->av_mutex); mutex_init(&dev_priv->wm.wm_mutex); mutex_init(&dev_priv->pps_mutex); + mutex_init(&dev_priv->gmbus_mutex); i915_memcpy_init_early(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 0f0aea900ceb..ebfafef7bf88 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2078,6 +2078,9 @@ void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, void intel_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_state *cdclk_state) { + struct intel_encoder *encoder; + unsigned int aux_mutex_lockclass = 0; + if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) return; @@ -2086,8 +2089,30 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to"); + /* + * Lock aux/gmbus while we change cdclk in case the + * those functions use cdclk. Not all platforms/ports + * do, but we'll lock them all for simplicity. All other + * users of cdclk (apart from audio) should be off on + * account of the pipes being off. + */ + for_each_intel_dp(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + + mutex_lock_nested(&intel_dp->aux.hw_mutex, + aux_mutex_lockclass++); + } + mutex_lock(&dev_priv->gmbus_mutex); + dev_priv->display.set_cdclk(dev_priv, cdclk_state); + for_each_intel_dp(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + + mutex_unlock(&intel_dp->aux.hw_mutex); + } + mutex_unlock(&dev_priv->gmbus_mutex); + if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), "cdclk state doesn't match!\n")) { intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 61729bf84e08..14bc8889596e 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -781,7 +781,6 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) i915_mmio_reg_offset(PCH_GPIOA) - i915_mmio_reg_offset(GPIOA); - mutex_init(&dev_priv->gmbus_mutex); init_waitqueue_head(&dev_priv->gmbus_wait_queue); for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {