| Message ID | 1529639712-23478-1-git-send-email-yakui.zhao@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Patchwork (2018-06-22 05:24:34) > == Series Details == > > Series: drm/i915: Use I915_MAP_WC for execlists context buffer on the platforms without LLC > URL : https://patchwork.freedesktop.org/series/45213/ > State : failure > > == Summary == > > = CI Bug Log - changes from CI_DRM_4368 -> Patchwork_9391 = > > == Summary - FAILURE == > > Serious unknown changes coming with Patchwork_9391 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_9391, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://patchwork.freedesktop.org/api/1.0/series/45213/revisions/1/mbox/ > > == Possible new issues == > > Here are the unknown changes that may have been introduced in Patchwork_9391: > > === IGT changes === > > ==== Possible regressions ==== > > igt@gem_close_race@basic-threads: > fi-bsw-n3050: PASS -> INCOMPLETE > > > == Known issues == > > Here are the changes found in Patchwork_9391 that come from known issues: > > === IGT changes === > > ==== Issues hit ==== > > igt@gem_close_race@basic-threads: > fi-glk-j4005: PASS -> INCOMPLETE (k.org#198133, fdo#103359) > fi-bxt-j4205: PASS -> INCOMPLETE (fdo#103927) > fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927) Iow, we've never encountered a failure to map the context image before. -Chris
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 10deebe..a76ea83 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1386,6 +1386,7 @@ __execlists_context_pin(struct intel_engine_cs *engine, { void *vaddr; int ret; + enum i915_map_type map = HAS_LLC(ctx->i915) ? I915_MAP_WB : I915_MAP_WC; ret = execlists_context_deferred_alloc(ctx, engine, ce); if (ret) @@ -1396,7 +1397,7 @@ __execlists_context_pin(struct intel_engine_cs *engine, if (ret) goto err; - vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); + vaddr = i915_gem_object_pin_map(ce->state->obj, map); if (IS_ERR(vaddr)) { ret = PTR_ERR(vaddr); goto unpin_vma; @@ -2728,6 +2729,7 @@ populate_lr_context(struct i915_gem_context *ctx, struct intel_engine_cs *engine, struct intel_ring *ring) { + enum i915_map_type map = HAS_LLC(ctx->i915) ? I915_MAP_WB : I915_MAP_WC; void *vaddr; u32 *regs; int ret; @@ -2738,7 +2740,7 @@ populate_lr_context(struct i915_gem_context *ctx, return ret; } - vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); + vaddr = i915_gem_object_pin_map(ctx_obj, map); if (IS_ERR(vaddr)) { ret = PTR_ERR(vaddr); DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); @@ -2756,7 +2758,7 @@ populate_lr_context(struct i915_gem_context *ctx, void *defaults; defaults = i915_gem_object_pin_map(engine->default_state, - I915_MAP_WB); + map); if (IS_ERR(defaults)) { ret = PTR_ERR(defaults); goto err_unpin_ctx;
Under execlists mode the context buffer is allocated in global Gtt region. The I915_MAP_WB type is used to map the buffer so that the driver can initialize the context buffer.(Ring reg, Context Ctrl reg and so on). And then __context_pin is called to flush back corresponding contents. In fact as it also tries to update context buffer (Ring Tail offset) before writting the ELSP port, it has no explicit cache flsuh.Maybe it is handled by HW. But this is quite confusing as BXT has no LLC. So the WC is used to map the context buffer on the platform without LLC and the update of context buffer is writen into phys page directly. It will be safer. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> CC: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_lrc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)