From patchwork Fri Jun 22 03:55:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhao, Yakui" X-Patchwork-Id: 10481177 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 008D760380 for ; Fri, 22 Jun 2018 03:56:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E770C28F91 for ; Fri, 22 Jun 2018 03:56:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DC17728F98; Fri, 22 Jun 2018 03:56:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5616028F91 for ; Fri, 22 Jun 2018 03:56:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A23F96E321; Fri, 22 Jun 2018 03:56:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 376A16E321 for ; Fri, 22 Jun 2018 03:56:15 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Jun 2018 20:56:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,255,1526367600"; d="scan'208";a="49644878" Received: from genxtest-ykzhao.sh.intel.com ([10.239.142.219]) by fmsmga008.fm.intel.com with ESMTP; 21 Jun 2018 20:56:12 -0700 From: Zhao Yakui To: intel-gfx@lists.freedesktop.org Date: Fri, 22 Jun 2018 11:55:12 +0800 Message-Id: <1529639712-23478-1-git-send-email-yakui.zhao@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH] drm/i915: Use I915_MAP_WC for execlists context buffer on the platforms without LLC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Under execlists mode the context buffer is allocated in global Gtt region. The I915_MAP_WB type is used to map the buffer so that the driver can initialize the context buffer.(Ring reg, Context Ctrl reg and so on). And then __context_pin is called to flush back corresponding contents. In fact as it also tries to update context buffer (Ring Tail offset) before writting the ELSP port, it has no explicit cache flsuh.Maybe it is handled by HW. But this is quite confusing as BXT has no LLC. So the WC is used to map the context buffer on the platform without LLC and the update of context buffer is writen into phys page directly. It will be safer. Signed-off-by: Zhao Yakui CC: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 10deebe..a76ea83 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1386,6 +1386,7 @@ __execlists_context_pin(struct intel_engine_cs *engine, { void *vaddr; int ret; + enum i915_map_type map = HAS_LLC(ctx->i915) ? I915_MAP_WB : I915_MAP_WC; ret = execlists_context_deferred_alloc(ctx, engine, ce); if (ret) @@ -1396,7 +1397,7 @@ __execlists_context_pin(struct intel_engine_cs *engine, if (ret) goto err; - vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); + vaddr = i915_gem_object_pin_map(ce->state->obj, map); if (IS_ERR(vaddr)) { ret = PTR_ERR(vaddr); goto unpin_vma; @@ -2728,6 +2729,7 @@ populate_lr_context(struct i915_gem_context *ctx, struct intel_engine_cs *engine, struct intel_ring *ring) { + enum i915_map_type map = HAS_LLC(ctx->i915) ? I915_MAP_WB : I915_MAP_WC; void *vaddr; u32 *regs; int ret; @@ -2738,7 +2740,7 @@ populate_lr_context(struct i915_gem_context *ctx, return ret; } - vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); + vaddr = i915_gem_object_pin_map(ctx_obj, map); if (IS_ERR(vaddr)) { ret = PTR_ERR(vaddr); DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); @@ -2756,7 +2758,7 @@ populate_lr_context(struct i915_gem_context *ctx, void *defaults; defaults = i915_gem_object_pin_map(engine->default_state, - I915_MAP_WB); + map); if (IS_ERR(defaults)) { ret = PTR_ERR(defaults); goto err_unpin_ctx;