From patchwork Tue Jul 3 02:22:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhao, Yakui" X-Patchwork-Id: 10502829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A1FC16028F for ; Tue, 3 Jul 2018 02:22:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8381128B5A for ; Tue, 3 Jul 2018 02:22:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75F5828B60; Tue, 3 Jul 2018 02:22:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1762928B5A for ; Tue, 3 Jul 2018 02:22:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3438D89CAC; Tue, 3 Jul 2018 02:22:38 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id CA9C189CB3 for ; Tue, 3 Jul 2018 02:22:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Jul 2018 19:22:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,301,1526367600"; d="scan'208";a="52197399" Received: from genxtest-ykzhao.sh.intel.com ([10.239.142.219]) by fmsmga008.fm.intel.com with ESMTP; 02 Jul 2018 19:22:35 -0700 From: Zhao Yakui To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Jul 2018 10:22:28 +0800 Message-Id: <1530584549-31867-2-git-send-email-yakui.zhao@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530584549-31867-1-git-send-email-yakui.zhao@intel.com> References: <1530584549-31867-1-git-send-email-yakui.zhao@intel.com> Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Use 64-bit to Read/Write fence reg on SNB+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Based on HW spec the fence reg on SNB+ is defined as 64-bit. Just follow the b-spec to use 64-bit read/write mode. Signed-off-by: Zhao Yakui --- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index d548ac0..d92fe03 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -63,6 +63,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence, i915_reg_t fence_reg_lo, fence_reg_hi; int fence_pitch_shift; u64 val; + struct drm_i915_private *dev_priv = fence->i915; if (INTEL_GEN(fence->i915) >= 6) { fence_reg_lo = FENCE_REG_GEN6_LO(fence->id); @@ -92,9 +93,14 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence, val |= I965_FENCE_REG_VALID; } - if (!pipelined) { - struct drm_i915_private *dev_priv = fence->i915; + if (INTEL_GEN(fence->i915) >= 6) { + /* Use the 64-bit RW to read/write fence reg on SNB+ */ + I915_WRITE64_FW(fence_reg_lo, 0); + I915_READ64(fence_reg_lo); + I915_WRITE64_FW(fence_reg_lo, val); + I915_READ64(fence_reg_lo); + } else { /* To w/a incoherency with non-atomic 64-bit register updates, * we split the 64-bit update into two 32-bit writes. In order * for a partial fence not to be evaluated between writes, we