From patchwork Tue Jul 3 12:47:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chauhan, Madhav" X-Patchwork-Id: 10504031 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EF993602BC for ; Tue, 3 Jul 2018 12:57:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DFE2C289DD for ; Tue, 3 Jul 2018 12:57:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D4A79289EE; Tue, 3 Jul 2018 12:57:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9377A289DD for ; Tue, 3 Jul 2018 12:57:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 39A9C6E6B3; Tue, 3 Jul 2018 12:57:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id BDF9E6E315 for ; Tue, 3 Jul 2018 12:57:43 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Jul 2018 05:57:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,303,1526367600"; d="scan'208";a="69287336" Received: from madhav-desktop.iind.intel.com ([10.223.25.13]) by fmsmga001.fm.intel.com with ESMTP; 03 Jul 2018 05:57:38 -0700 From: Madhav Chauhan To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Jul 2018 18:17:40 +0530 Message-Id: <1530622074-28307-7-git-send-email-madhav.chauhan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530622074-28307-1-git-send-email-madhav.chauhan@intel.com> References: <1530622074-28307-1-git-send-email-madhav.chauhan@intel.com> Subject: [Intel-gfx] [PATCH v2 06/20] drm/i915/icl: Power down unused DSI lanes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To save power, unused lanes should be powered down using the bitfield of PORT_CL_DW10. v2: Review comments from Jani N - Put default label next to case 4 - Include the shifts in the macros Signed-off-by: Madhav Chauhan Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dsi_new.c | 40 ++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c index 64f97c7..9262e3f 100644 --- a/drivers/gpu/drm/i915/intel_dsi_new.c +++ b/drivers/gpu/drm/i915/intel_dsi_new.c @@ -74,6 +74,43 @@ static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) } } +static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + enum port port; + u32 tmp; + u32 lane_mask; + + switch (intel_dsi->lane_count) { + case 1: + lane_mask = PWR_DOWN_LN_3_1_0; + break; + case 2: + lane_mask = PWR_DOWN_LN_3_1; + break; + case 3: + lane_mask = PWR_DOWN_LN_3; + break; + case 4: + default: + lane_mask = PWR_UP_ALL_LANES; + break; + } + + for_each_dsi_port(port, intel_dsi->ports) { + tmp = I915_READ(ICL_PORT_CL_DW10(port)); + tmp &= ~PWR_DOWN_LN_MASK; + I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask); + } +} + +static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder) +{ + /* step 4a: power up all lanes of the DDI used by DSI */ + gen11_dsi_power_up_lanes(encoder); +} + static void __attribute__((unused)) gen11_dsi_pre_enable(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, @@ -84,4 +121,7 @@ gen11_dsi_pre_enable(struct intel_encoder *encoder, /* step3: enable DSI PLL */ gen11_dsi_program_esc_clk_div(encoder); + + /* step4: enable DSI port and DPHY */ + gen11_dsi_enable_port_and_phy(encoder); }