From patchwork Thu Jul 5 13:49:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chauhan, Madhav" X-Patchwork-Id: 10509383 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C3D0A60116 for ; Thu, 5 Jul 2018 14:00:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B4716290FE for ; Thu, 5 Jul 2018 14:00:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B266C2914C; Thu, 5 Jul 2018 14:00:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 59A8A29136 for ; Thu, 5 Jul 2018 14:00:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BAE206EDAC; Thu, 5 Jul 2018 14:00:06 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id CF2056EDAC for ; Thu, 5 Jul 2018 14:00:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jul 2018 07:00:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,312,1526367600"; d="scan'208";a="242852875" Received: from madhav-desktop.iind.intel.com ([10.223.25.13]) by fmsmga005.fm.intel.com with ESMTP; 05 Jul 2018 07:00:03 -0700 From: Madhav Chauhan To: intel-gfx@lists.freedesktop.org Date: Thu, 5 Jul 2018 19:19:50 +0530 Message-Id: <1530798591-2077-20-git-send-email-madhav.chauhan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530798591-2077-1-git-send-email-madhav.chauhan@intel.com> References: <1530798591-2077-1-git-send-email-madhav.chauhan@intel.com> Subject: [Intel-gfx] [PATCH v4 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch defines transcoder function configuration registers and its bitfields for both DSI ports. Used while programming/enabling DSI transcoder. Signed-off-by: Madhav Chauhan --- drivers/gpu/drm/i915/i915_reg.h | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a15587b..27be943 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10118,6 +10118,53 @@ enum skl_power_gate { #define TA_SURE_TIME(x) (x << 16) #define TA_SURE_TIME_MASK (0x1f << 16) +/* DSI transcoder configuration */ +#define _DSI_TRANS_FUNC_CONF_0 0x6b030 +#define _DSI_TRANS_FUNC_CONF_1 0x6b830 +#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ + _DSI_TRANS_FUNC_CONF_0,\ + _DSI_TRANS_FUNC_CONF_1) +#define OP_MODE(x) (x << 28) +#define OP_MODE_MASK (0x3 << 28) +#define CMD_MODE_NO_GATE 0x0 +#define CMD_MODE_TE_GATE 0x1 +#define VIDEO_MODE_SYNC_EVENT 0x2 +#define VIDEO_MODE_SYNC_PULSE 0x3 +#define LINK_READY (1 << 20) +#define PIX_FMT(x) (x << 16) +#define PIX_FMT_MASK (0x3 << 16) +#define PIX_FMT_RGB565 0x0 +#define PIX_FMT_RGB666_PACKED 0x1 +#define PIX_FMT_RGB666_LOOSE 0x2 +#define PIX_FMT_RGB888 0x3 +#define PIX_FMT_RGB101010 0x4 +#define PIX_FMT_RGB121212 0x5 +#define PIX_FMT_COMPRESSED 0x6 +#define BGR_TRANSMISSION (1 << 15) +#define PIX_VIRT_CHAN(x) (x << 12) +#define PIX_VIRT_CHAN_MASK (0x3 << 12) +#define PIX_BUF_THRESHOLD(x) ((x & 0x3) << 10) +#define PIX_BUF_THRESHOLD_MASK (0x3 << 10) +#define PIX_BUF_THRESHOLD_1_4 0x0 +#define PIX_BUF_THRESHOLD_1_2 0x1 +#define PIX_BUF_THRESHOLD_3_4 0x2 +#define PIX_BUF_THRESHOLD_FULL 0x3 +#define CONTINUOUS_CLK(x) (x << 8) +#define CONTINUOUS_CLK_MASK (0x3 << 8) +#define CLK_ENTER_LP_AFTER_DATA 0x0 +#define CLK_HS_OR_LP 0x2 +#define CLK_HS_CONTINUOUS 0x3 +#define LINK_CALIBRATION(x) (x << 4) +#define LINK_CALIBRATION_MASK (0x3 << 4) +#define CALIBRATION_DISABLED 0x0 +#define CALIBRATION_ENABLED_INITIAL_ONLY 0x2 +#define CALIBRATION_ENABLED_INITIAL_PERIODIC 0x3 +#define S3D_ORIENTATION(x) (x << 1) +#define S3D_ORIENTATION_MASK (0x1 << 1) +#define S3D_ORIENTATION_PORTRAIT 0x0 +#define S3D_ORIENTATION_LANDSCAPE 0x1 +#define EOTP_DISABLED (1 << 0) + /* bits 31:0 */ #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)