Message ID | 1533003183-22793-15-git-send-email-manasi.d.navare@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Enable Display Stream Compression on eDP/DP | expand |
>-----Original Message----- >From: Navare, Manasi D >Sent: Monday, July 30, 2018 7:13 PM >To: intel-gfx@lists.freedesktop.org >Cc: ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; Srivatsa, Anusha ><anusha.srivatsa@intel.com>; Singh, Gaurav K <gaurav.k.singh@intel.com>; dri- >devel@lists.freedesktop.org; Navare, Manasi D <manasi.d.navare@intel.com> >Subject: [PATCH 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth >constants > >From: Gaurav K Singh <gaurav.k.singh@intel.com> > >DSC specification defines linebuf_depth which contains the line buffer bit depth >used to generate the bitstream. >These values are defined as per Table 4.1 in DSC 1.2 spec > >v2 (From Manasi): >* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2 > >Cc: dri-devel@lists.freedesktop.org >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> >Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > include/drm/drm_dsc.h | 3 +++ > 1 file changed, 3 insertions(+) > >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index >30adc15..4cfcd03 100644 >--- a/include/drm/drm_dsc.h >+++ b/include/drm/drm_dsc.h >@@ -56,6 +56,9 @@ > #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 > #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 > #define DSC_PPS_NATIVE_420_SHIFT 1 >+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 >+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 >+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 > > /* Configuration for a single Rate Control model range */ struct >dsc_rc_range_parameters { >-- >2.7.4
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index 30adc15..4cfcd03 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -56,6 +56,9 @@ #define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 #define DSC_PPS_NATIVE_420_SHIFT 1 +#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 +#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 +#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 /* Configuration for a single Rate Control model range */ struct dsc_rc_range_parameters {