diff mbox series

[v2,10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes

Message ID 1533071239-28815-11-git-send-email-manasi.d.navare@intel.com (mailing list archive)
State New, archived
Headers show
Series Display Stream Compression enabling on eDP/DP | expand

Commit Message

Navare, Manasi July 31, 2018, 9:07 p.m. UTC 
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.

v5:
Do not use bitfields for DRM structs (Jani N)
v4:
* Use DSC constants for params that dont change across
configurations
v3:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)

v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 Documentation/gpu/drm-kms-helpers.rst |  12 ++
 drivers/gpu/drm/Makefile              |   2 +-
 drivers/gpu/drm/drm_dsc.c             | 221 ++++++++++++++++++++++++++++++++++
 include/drm/drm_dsc.h                 |  22 ++++
 4 files changed, 256 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_dsc.c

Comments

Chris Wilson July 31, 2018, 9:16 p.m. UTC | #1 
Quoting Manasi Navare (2018-07-31 22:07:06)
> +       /* PPS 4 */
> +       pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> +                                          DSC_PPS_BPP_HIGH_MASK) >>
> +                                         DSC_PPS_MSB_SHIFT) |

To avoid overhanging cliffs, insert the newline after the sequence
point. Quite a few examples throughout the series that would benefit
from more judicial placement of line breaks.

> +               (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> +               (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> +               (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> +               (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;

Furthermore, you only need the SPDX shorthand rather than full licence
text.
-Chris
Navare, Manasi Aug. 3, 2018, 7:18 p.m. UTC | #2 
On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote:
> Quoting Manasi Navare (2018-07-31 22:07:06)
> > +       /* PPS 4 */
> > +       pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> > +                                          DSC_PPS_BPP_HIGH_MASK) >>
> > +                                         DSC_PPS_MSB_SHIFT) |
> 
> To avoid overhanging cliffs, insert the newline after the sequence
> point. Quite a few examples throughout the series that would benefit
> from more judicial placement of line breaks.

What exactly are you refering to by sequence point here?
I am adding newline here after the operator if the next operand exceeds the 80 column limit.

> 
> > +               (u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> > +               (u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> > +               (u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> > +               (u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
> 
> Furthermore, you only need the SPDX shorthand rather than full licence
> text.

Here the header is what all the other .c files in drm have. They all tend to use
complete text.
Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file?
Should I remove the entire paragraph about the Copyright?

Manasi

> -Chris
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
Chris Wilson Aug. 3, 2018, 7:43 p.m. UTC | #3 
Quoting Manasi Navare (2018-08-03 20:18:42)
> On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote:
> > Quoting Manasi Navare (2018-07-31 22:07:06)
> > > +       /* PPS 4 */
> > > +       pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> > > +                                          DSC_PPS_BPP_HIGH_MASK) >>
> > > +                                         DSC_PPS_MSB_SHIFT) |
> > 
> > To avoid overhanging cliffs, insert the newline after the sequence
> > point. Quite a few examples throughout the series that would benefit
> > from more judicial placement of line breaks.
> 
> What exactly are you refering to by sequence point here?

Which ever makes sense visually, here '='.

pps_sdp->pps_payload.pps_4 =
	dsc_cfg->bits_per_pixel >> X << DSC_PPS_MSB_SHIFT |
	dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
	dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
	dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
	dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;

If you want to mask with 0xff do it without having to refer to C type promotion
rules.

> > Furthermore, you only need the SPDX shorthand rather than full licence
> > text.
> 
> Here the header is what all the other .c files in drm have. They all tend to use
> complete text.

And they all need updating, eventually. There's no reason for new file
to use the old style.

> Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file?
> Should I remove the entire paragraph about the Copyright?

No, the code is MIT. You replace the licence with just a SPDX link.
-Chris
Navare, Manasi Aug. 3, 2018, 7:55 p.m. UTC | #4 
On Fri, Aug 03, 2018 at 08:43:51PM +0100, Chris Wilson wrote:
> Quoting Manasi Navare (2018-08-03 20:18:42)
> > On Tue, Jul 31, 2018 at 10:16:45PM +0100, Chris Wilson wrote:
> > > Quoting Manasi Navare (2018-07-31 22:07:06)
> > > > +       /* PPS 4 */
> > > > +       pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> > > > +                                          DSC_PPS_BPP_HIGH_MASK) >>
> > > > +                                         DSC_PPS_MSB_SHIFT) |
> > > 
> > > To avoid overhanging cliffs, insert the newline after the sequence
> > > point. Quite a few examples throughout the series that would benefit
> > > from more judicial placement of line breaks.
> > 
> > What exactly are you refering to by sequence point here?
> 
> Which ever makes sense visually, here '='.
> 
> pps_sdp->pps_payload.pps_4 =
> 	dsc_cfg->bits_per_pixel >> X << DSC_PPS_MSB_SHIFT |
> 	dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> 	dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> 	dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> 	dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;

Ok understood about the sequence point

> 
> If you want to mask with 0xff do it without having to refer to C type promotion
> rules.

This point is still not clear. is this not correct:
(dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> DSC_PPS_MSB_SHIFT

> 
> > > Furthermore, you only need the SPDX shorthand rather than full licence
> > > text.
> > 
> > Here the header is what all the other .c files in drm have. They all tend to use
> > complete text.
> 
> And they all need updating, eventually. There's no reason for new file
> to use the old style.
> 
> > Are you suggesting just adding SPDX-License-Identifier: GPL-2.0+ at the begining of the file?
> > Should I remove the entire paragraph about the Copyright?
> 
> No, the code is MIT. You replace the licence with just a SPDX link.

Could you give an example here for the correct way of adding SPDX info in the header and what part
of the existing header needs to stay?
That would be helpful.

Manasi
> -Chris
Harry Wentland Aug. 23, 2018, 7:58 p.m. UTC | #5 
On 2018-07-31 05:07 PM, Manasi Navare wrote:
> According to Display Stream compression spec 1.2, the picture
> parameter set metadata is sent from source to sink device
> using the DP Secondary data packet. An infoframe is formed
> for the PPS SDP header and PPS SDP payload bytes.
> This patch adds helpers to fill the PPS SDP header
> and PPS SDP payload according to the DSC 1.2 specification.
> 
> v5:
> Do not use bitfields for DRM structs (Jani N)
> v4:
> * Use DSC constants for params that dont change across
> configurations
> v3:
> * Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
> (Daniel Vetter)
> 
> v2:
> * Add EXPORT_SYMBOL for the drm functions (Manasi)
> 
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>

Acked-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  Documentation/gpu/drm-kms-helpers.rst |  12 ++
>  drivers/gpu/drm/Makefile              |   2 +-
>  drivers/gpu/drm/drm_dsc.c             | 221 ++++++++++++++++++++++++++++++++++
>  include/drm/drm_dsc.h                 |  22 ++++
>  4 files changed, 256 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/drm_dsc.c
> 
> diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
> index f9cfcdc..50bb717 100644
> --- a/Documentation/gpu/drm-kms-helpers.rst
> +++ b/Documentation/gpu/drm-kms-helpers.rst
> @@ -223,6 +223,18 @@ MIPI DSI Helper Functions Reference
>  .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
>     :export:
>  
> +Display Stream Compression Helper Functions Reference
> +=====================================================
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
> +   :doc: dsc helpers
> +
> +.. kernel-doc:: include/drm/drm_dsc.h
> +   :internal:
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
> +   :export:
> +
>  Output Probing Helper Functions Reference
>  =========================================
>  
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index a6771ce..961e511 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
>  drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
>  drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
>  
> -drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
> +drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \
>  		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
>  		drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
>  		drm_simple_kms_helper.o drm_modeset_helper.o \
> diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
> new file mode 100644
> index 0000000..99a8794
> --- /dev/null
> +++ b/drivers/gpu/drm/drm_dsc.c
> @@ -0,0 +1,221 @@
> +/*
> + *Copyright © 2018 Intel Corp
> + *
> + * Permission to use, copy, modify, distribute, and sell this software and its
> + * documentation for any purpose is hereby granted without fee, provided that
> + * the above copyright notice appear in all copies and that both that copyright
> + * notice and this permission notice appear in supporting documentation, and
> + * that the name of the copyright holders not be used in advertising or
> + * publicity pertaining to distribution of the software without specific,
> + * written prior permission.  The copyright holders make no representations
> + * about the suitability of this software for any purpose.  It is provided "as
> + * is" without express or implied warranty.
> + *
> + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
> + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
> + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
> + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
> + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
> + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
> + * OF THIS SOFTWARE.
> + *
> + * Author:
> + * Manasi Navare <manasi.d.navare@intel.com>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <drm/drm_dp_helper.h>
> +#include <drm/drm_dsc.h>
> +
> +/**
> + * DOC: dsc helpers
> + *
> + * These functions contain some common logic and helpers to deal with VESA
> + * Display Stream Compression standard required for DSC on Display Port/eDP or
> + * MIPI display interfaces.
> + */
> +
> +/**
> + * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
> + * for DisplayPort as per the DP 1.4 spec.
> + * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
> + */
> +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
> +{
> +	memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
> +
> +	pps_sdp->pps_header.HB1 = DP_SDP_PPS;
> +	pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
> +}
> +EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
> +
> +/**
> + * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
> + * using the DSC configuration parameters in the order expected
> + * by the DSC Display Sink device. For the DSC, the sink device
> + * expects the PPS payload in the big endian format for the fields
> + * that span more than 1 byte.
> + *
> + * @pps_sdp:
> + * Secondary data packet for DSC Picture Parameter Set
> + * @dsc_cfg:
> + * DSC Configuration data filled by driver
> + */
> +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> +				struct drm_dsc_config *dsc_cfg)
> +{
> +	u8 i = 0;
> +
> +	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
> +
> +	/* PPS 0 */
> +	pps_sdp->pps_payload.dsc_version = dsc_cfg->dsc_version_minor |
> +		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
> +
> +	/* PPS 1, 2 is 0 */
> +
> +	/* PPS 3 */
> +	pps_sdp->pps_payload.pps_3 = dsc_cfg->line_buf_depth |
> +		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
> +
> +	/* PPS 4 */
> +	pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
> +					   DSC_PPS_BPP_HIGH_MASK) >>
> +					  DSC_PPS_MSB_SHIFT) |
> +		(u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
> +		(u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
> +		(u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
> +		(u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
> +
> +	/* PPS 5 */
> +	pps_sdp->pps_payload.bits_per_pixel_low = (u8)(dsc_cfg->bits_per_pixel &
> +						       DSC_PPS_LSB_MASK);
> +
> +	/*
> +	 * The DSC panel expects the PPS packet to have big endian format
> +	 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
> +	 * to big endian format. If format is little endian, it will swap
> +	 * bytes to convert to Big endian else keep it unchanged.
> +	 */
> +
> +	/* PPS 6, 7 */
> +	pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
> +
> +	/* PPS 8, 9 */
> +	pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
> +
> +	/* PPS 10, 11 */
> +	pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
> +
> +	/* PPS 12, 13 */
> +	pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
> +
> +	/* PPS 14, 15 */
> +	pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
> +
> +	/* PPS 16 */
> +	pps_sdp->pps_payload.initial_xmit_delay_high = (u8)((dsc_cfg->initial_xmit_delay &
> +							     DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
> +							    DSC_PPS_MSB_SHIFT);
> +
> +	/* PPS 17 */
> +	pps_sdp->pps_payload.initial_xmit_delay_low = (u8)(dsc_cfg->initial_xmit_delay &
> +							   DSC_PPS_LSB_MASK);
> +
> +	/* PPS 18, 19 */
> +	pps_sdp->pps_payload.initial_dec_delay = cpu_to_be16(dsc_cfg->initial_dec_delay);
> +
> +	/* PPS 20 is 0 */
> +
> +	/* PPS 21 */
> +	pps_sdp->pps_payload.initial_scale_value = (u8)dsc_cfg->initial_scale_value;
> +
> +	/* PPS 22, 23 */
> +	pps_sdp->pps_payload.scale_increment_interval = cpu_to_be16(dsc_cfg->scale_increment_interval);
> +
> +	/* PPS 24 */
> +	pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &
> +								   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
> +								  DSC_PPS_MSB_SHIFT);
> +
> +	/* PPS 25 */
> +	pps_sdp->pps_payload.scale_decrement_interval_low = (u8)(dsc_cfg->scale_decrement_interval &
> +								 DSC_PPS_LSB_MASK);
> +
> +	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
> +
> +	/* PPS 27 */
> +	pps_sdp->pps_payload.first_line_bpg_offset = (u8)dsc_cfg->first_line_bpg_offset;
> +
> +	/* PPS 28, 29 */
> +	pps_sdp->pps_payload.nfl_bpg_offset = cpu_to_be16(dsc_cfg->nfl_bpg_offset);
> +
> +	/* PPS 30, 31 */
> +	pps_sdp->pps_payload.slice_bpg_offset = cpu_to_be16(dsc_cfg->slice_bpg_offset);
> +
> +	/* PPS 32, 33 */
> +	pps_sdp->pps_payload.initial_offset = cpu_to_be16(dsc_cfg->initial_offset);
> +
> +	/* PPS 34, 35 */
> +	pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
> +
> +	/* PPS 36 */
> +	pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp;
> +
> +	/* PPS 37 */
> +	pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp;
> +
> +	/* PPS 38, 39 */
> +	pps_sdp->pps_payload.rc_model_size = cpu_to_be16((u16)DSC_RC_MODEL_SIZE_CONST);
> +
> +	/* PPS 40 */
> +	pps_sdp->pps_payload.rc_edge_factor = (u8)DSC_RC_EDGE_FACTOR_CONST;
> +
> +	/* PPS 41 */
> +	pps_sdp->pps_payload.rc_quant_incr_limit0 = (u8)dsc_cfg->rc_quant_incr_limit0;
> +
> +	/* PPS 42 */
> +	pps_sdp->pps_payload.rc_quant_incr_limit1 = (u8)dsc_cfg->rc_quant_incr_limit1;
> +
> +	/* PPS 43 */
> +	pps_sdp->pps_payload.rc_tgt_offset = (u8)DSC_RC_TGT_OFFSET_LO_CONST |
> +		(u8)DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
> +
> +	/* PPS 44 - 57 */
> +	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
> +		pps_sdp->pps_payload.rc_buf_thresh[i] = dsc_cfg->rc_buf_thresh[i];
> +
> +	/* PPS 58 - 87 */
> +	/*
> +	 * For DSC sink programming the RC Range parameter fields
> +	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
> +	 */
> +	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> +		pps_sdp->pps_payload.rc_range_parameters[i] =
> +			(u16)((dsc_cfg->rc_range_params[i].range_min_qp <<
> +			       DSC_PPS_RC_RANGE_MINQP_SHIFT) |
> +			      (dsc_cfg->rc_range_params[i].range_max_qp <<
> +			       DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
> +			      (dsc_cfg->rc_range_params[i].range_bpg_offset));
> +		pps_sdp->pps_payload.rc_range_parameters[i] = cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
> +	}
> +
> +	/* PPS 88 */
> +	pps_sdp->pps_payload.native_422_420 = (u8)dsc_cfg->native_422 |
> +		(u8)dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
> +
> +	/* PPS 89 */
> +	pps_sdp->pps_payload.second_line_bpg_offset = (u8)dsc_cfg->second_line_bpg_offset;
> +
> +	/* PPS 90, 91 */
> +	pps_sdp->pps_payload.nsl_bpg_offset = cpu_to_be16(dsc_cfg->nsl_bpg_offset);
> +
> +	/* PPS 92, 93 */
> +	pps_sdp->pps_payload.second_line_offset_adj = cpu_to_be16(dsc_cfg->second_line_offset_adj);
> +
> +	/* PPS 94 - 127 are O */
> +}
> +EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index ebd99d7..30adc15 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -26,6 +26,7 @@
>  #ifndef DRM_DSC_H_
>  #define DRM_DSC_H_
>  
> +#include <linux/byteorder/generic.h>
>  #include <drm/drm_dp_helper.h>
>  
>  /* VESA Display Stream Compression DSC 1.2 constants */
> @@ -39,6 +40,23 @@
>  #define DSC_RC_TGT_OFFSET_HI_CONST	    3
>  #define DSC_RC_TGT_OFFSET_LO_CONST	    3
>  
> +/* DSC PPS constants and macros */
> +#define DSC_PPS_VERSION_MAJOR_SHIFT		4
> +#define DSC_PPS_BPC_SHIFT			4
> +#define DSC_PPS_MSB_SHIFT			8
> +#define DSC_PPS_LSB_MASK			(0xFF << 0)
> +#define DSC_PPS_BPP_HIGH_MASK			(0x3 << 8)
> +#define DSC_PPS_VBR_EN_SHIFT			2
> +#define DSC_PPS_SIMPLE422_SHIFT			3
> +#define DSC_PPS_CONVERT_RGB_SHIFT		4
> +#define DSC_PPS_BLOCK_PRED_EN_SHIFT		5
> +#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK	(0x3 << 8)
> +#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK		(0xF << 8)
> +#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT		4
> +#define DSC_PPS_RC_RANGE_MINQP_SHIFT		11
> +#define DSC_PPS_RC_RANGE_MAXQP_SHIFT		6
> +#define DSC_PPS_NATIVE_420_SHIFT		1
> +
>  /* Configuration for a single Rate Control model range */
>  struct dsc_rc_range_parameters {
>  	/* Min Quantization Parameters allowed for this range */
> @@ -478,4 +496,8 @@ struct drm_dsc_pps_infoframe {
>  	struct picture_parameter_set pps_payload;
>  } __packed;
>  
> +void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
> +void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
> +				struct drm_dsc_config *dsc_cfg);
> +
>  #endif /* _DRM_DSC_H_ */
> -- 2.7.4
>
diff mbox series

Patch

diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
index f9cfcdc..50bb717 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -223,6 +223,18 @@  MIPI DSI Helper Functions Reference
 .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
    :export:
 
+Display Stream Compression Helper Functions Reference
+=====================================================
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+   :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :export:
+
 Output Probing Helper Functions Reference
 =========================================
 
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index a6771ce..961e511 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -31,7 +31,7 @@  drm-$(CONFIG_AGP) += drm_agpsupport.o
 drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
 drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
 
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \
 		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
 		drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
 		drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index 0000000..99a8794
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,221 @@ 
+/*
+ *Copyright © 2018 Intel Corp
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Author:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_dsc.h>
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+	memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+	pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+	pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+				struct drm_dsc_config *dsc_cfg)
+{
+	u8 i = 0;
+
+	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+	/* PPS 0 */
+	pps_sdp->pps_payload.dsc_version = dsc_cfg->dsc_version_minor |
+		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
+
+	/* PPS 1, 2 is 0 */
+
+	/* PPS 3 */
+	pps_sdp->pps_payload.pps_3 = dsc_cfg->line_buf_depth |
+		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
+
+	/* PPS 4 */
+	pps_sdp->pps_payload.pps_4 = (u8)((dsc_cfg->bits_per_pixel &
+					   DSC_PPS_BPP_HIGH_MASK) >>
+					  DSC_PPS_MSB_SHIFT) |
+		(u8)dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
+		(u8)dsc_cfg->enable422 << DSC_PPS_SIMPLE422_SHIFT |
+		(u8)dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
+		(u8)dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
+
+	/* PPS 5 */
+	pps_sdp->pps_payload.bits_per_pixel_low = (u8)(dsc_cfg->bits_per_pixel &
+						       DSC_PPS_LSB_MASK);
+
+	/*
+	 * The DSC panel expects the PPS packet to have big endian format
+	 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
+	 * to big endian format. If format is little endian, it will swap
+	 * bytes to convert to Big endian else keep it unchanged.
+	 */
+
+	/* PPS 6, 7 */
+	pps_sdp->pps_payload.pic_height = cpu_to_be16(dsc_cfg->pic_height);
+
+	/* PPS 8, 9 */
+	pps_sdp->pps_payload.pic_width = cpu_to_be16(dsc_cfg->pic_width);
+
+	/* PPS 10, 11 */
+	pps_sdp->pps_payload.slice_height = cpu_to_be16(dsc_cfg->slice_height);
+
+	/* PPS 12, 13 */
+	pps_sdp->pps_payload.slice_width = cpu_to_be16(dsc_cfg->slice_width);
+
+	/* PPS 14, 15 */
+	pps_sdp->pps_payload.chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
+
+	/* PPS 16 */
+	pps_sdp->pps_payload.initial_xmit_delay_high = (u8)((dsc_cfg->initial_xmit_delay &
+							     DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
+							    DSC_PPS_MSB_SHIFT);
+
+	/* PPS 17 */
+	pps_sdp->pps_payload.initial_xmit_delay_low = (u8)(dsc_cfg->initial_xmit_delay &
+							   DSC_PPS_LSB_MASK);
+
+	/* PPS 18, 19 */
+	pps_sdp->pps_payload.initial_dec_delay = cpu_to_be16(dsc_cfg->initial_dec_delay);
+
+	/* PPS 20 is 0 */
+
+	/* PPS 21 */
+	pps_sdp->pps_payload.initial_scale_value = (u8)dsc_cfg->initial_scale_value;
+
+	/* PPS 22, 23 */
+	pps_sdp->pps_payload.scale_increment_interval = cpu_to_be16(dsc_cfg->scale_increment_interval);
+
+	/* PPS 24 */
+	pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &
+								   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
+								  DSC_PPS_MSB_SHIFT);
+
+	/* PPS 25 */
+	pps_sdp->pps_payload.scale_decrement_interval_low = (u8)(dsc_cfg->scale_decrement_interval &
+								 DSC_PPS_LSB_MASK);
+
+	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
+
+	/* PPS 27 */
+	pps_sdp->pps_payload.first_line_bpg_offset = (u8)dsc_cfg->first_line_bpg_offset;
+
+	/* PPS 28, 29 */
+	pps_sdp->pps_payload.nfl_bpg_offset = cpu_to_be16(dsc_cfg->nfl_bpg_offset);
+
+	/* PPS 30, 31 */
+	pps_sdp->pps_payload.slice_bpg_offset = cpu_to_be16(dsc_cfg->slice_bpg_offset);
+
+	/* PPS 32, 33 */
+	pps_sdp->pps_payload.initial_offset = cpu_to_be16(dsc_cfg->initial_offset);
+
+	/* PPS 34, 35 */
+	pps_sdp->pps_payload.final_offset = cpu_to_be16(dsc_cfg->final_offset);
+
+	/* PPS 36 */
+	pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp;
+
+	/* PPS 37 */
+	pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp;
+
+	/* PPS 38, 39 */
+	pps_sdp->pps_payload.rc_model_size = cpu_to_be16((u16)DSC_RC_MODEL_SIZE_CONST);
+
+	/* PPS 40 */
+	pps_sdp->pps_payload.rc_edge_factor = (u8)DSC_RC_EDGE_FACTOR_CONST;
+
+	/* PPS 41 */
+	pps_sdp->pps_payload.rc_quant_incr_limit0 = (u8)dsc_cfg->rc_quant_incr_limit0;
+
+	/* PPS 42 */
+	pps_sdp->pps_payload.rc_quant_incr_limit1 = (u8)dsc_cfg->rc_quant_incr_limit1;
+
+	/* PPS 43 */
+	pps_sdp->pps_payload.rc_tgt_offset = (u8)DSC_RC_TGT_OFFSET_LO_CONST |
+		(u8)DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
+
+	/* PPS 44 - 57 */
+	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
+		pps_sdp->pps_payload.rc_buf_thresh[i] = dsc_cfg->rc_buf_thresh[i];
+
+	/* PPS 58 - 87 */
+	/*
+	 * For DSC sink programming the RC Range parameter fields
+	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
+	 */
+	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+		pps_sdp->pps_payload.rc_range_parameters[i] =
+			(u16)((dsc_cfg->rc_range_params[i].range_min_qp <<
+			       DSC_PPS_RC_RANGE_MINQP_SHIFT) |
+			      (dsc_cfg->rc_range_params[i].range_max_qp <<
+			       DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
+			      (dsc_cfg->rc_range_params[i].range_bpg_offset));
+		pps_sdp->pps_payload.rc_range_parameters[i] = cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);
+	}
+
+	/* PPS 88 */
+	pps_sdp->pps_payload.native_422_420 = (u8)dsc_cfg->native_422 |
+		(u8)dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
+
+	/* PPS 89 */
+	pps_sdp->pps_payload.second_line_bpg_offset = (u8)dsc_cfg->second_line_bpg_offset;
+
+	/* PPS 90, 91 */
+	pps_sdp->pps_payload.nsl_bpg_offset = cpu_to_be16(dsc_cfg->nsl_bpg_offset);
+
+	/* PPS 92, 93 */
+	pps_sdp->pps_payload.second_line_offset_adj = cpu_to_be16(dsc_cfg->second_line_offset_adj);
+
+	/* PPS 94 - 127 are O */
+}
+EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index ebd99d7..30adc15 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -26,6 +26,7 @@ 
 #ifndef DRM_DSC_H_
 #define DRM_DSC_H_
 
+#include <linux/byteorder/generic.h>
 #include <drm/drm_dp_helper.h>
 
 /* VESA Display Stream Compression DSC 1.2 constants */
@@ -39,6 +40,23 @@ 
 #define DSC_RC_TGT_OFFSET_HI_CONST	    3
 #define DSC_RC_TGT_OFFSET_LO_CONST	    3
 
+/* DSC PPS constants and macros */
+#define DSC_PPS_VERSION_MAJOR_SHIFT		4
+#define DSC_PPS_BPC_SHIFT			4
+#define DSC_PPS_MSB_SHIFT			8
+#define DSC_PPS_LSB_MASK			(0xFF << 0)
+#define DSC_PPS_BPP_HIGH_MASK			(0x3 << 8)
+#define DSC_PPS_VBR_EN_SHIFT			2
+#define DSC_PPS_SIMPLE422_SHIFT			3
+#define DSC_PPS_CONVERT_RGB_SHIFT		4
+#define DSC_PPS_BLOCK_PRED_EN_SHIFT		5
+#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK	(0x3 << 8)
+#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK		(0xF << 8)
+#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT		4
+#define DSC_PPS_RC_RANGE_MINQP_SHIFT		11
+#define DSC_PPS_RC_RANGE_MAXQP_SHIFT		6
+#define DSC_PPS_NATIVE_420_SHIFT		1
+
 /* Configuration for a single Rate Control model range */
 struct dsc_rc_range_parameters {
 	/* Min Quantization Parameters allowed for this range */
@@ -478,4 +496,8 @@  struct drm_dsc_pps_infoframe {
 	struct picture_parameter_set pps_payload;
 } __packed;
 
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+				struct drm_dsc_config *dsc_cfg);
+
 #endif /* _DRM_DSC_H_ */