From patchwork Wed Aug 1 00:30:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 10551577 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E882514E0 for ; Wed, 1 Aug 2018 00:27:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D95AF2ACB2 for ; Wed, 1 Aug 2018 00:27:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CCB382AD1D; Wed, 1 Aug 2018 00:27:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6E6682ACB2 for ; Wed, 1 Aug 2018 00:27:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 45D9788F94; Wed, 1 Aug 2018 00:27:08 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9AB3E88F94 for ; Wed, 1 Aug 2018 00:27:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Jul 2018 17:27:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,429,1526367600"; d="scan'208";a="71553641" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.151]) by orsmga003.jf.intel.com with ESMTP; 31 Jul 2018 17:27:04 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Tue, 31 Jul 2018 17:30:04 -0700 Message-Id: <1533083404-3642-1-git-send-email-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH] drm/i915/icl: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paulo Zanoni MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In case of Legacy DP connector on TypeC port (C, D, E or F), the flex IO DPMLE register is set to maximum number of lanes since there is no muxing with other controllers in this case. While in case of the TypeC connector, it is set to the lane count obained from DFLEXDPSP register. This needs to be programmed before enabling the shared PLLs hence add a pre_pll_enable hook for ICL and add this programming in that hook. v3: * Call intel_dp_max_common_lane_count that gets lane count common between sink, source, fia v2: * Add pre pll enable hook and move dflexdpmle programming to that hook (Animesh) Cc: Jani Nikula Cc: Animesh Manna Cc: Anusha Srivatsa Cc: Paulo Zanoni Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 0adc043..eb00ac4 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3193,6 +3193,22 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, bxt_ddi_phy_set_lane_optim_mask(encoder, mask); } +static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config, + const struct drm_connector_state *conn_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); + enum tc_port tc_port = intel_port_to_tc(dev_priv, + intel_dig_port->base.port); + + if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT) + return; + + intel_dp_set_fia_lane_count(intel_dp); +} + void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); @@ -3709,6 +3725,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) intel_encoder->enable = intel_enable_ddi; if (IS_GEN9_LP(dev_priv)) intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable; + if (IS_ICELAKE(dev_priv)) + intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable; intel_encoder->pre_enable = intel_ddi_pre_enable; intel_encoder->disable = intel_disable_ddi; intel_encoder->post_disable = intel_ddi_post_disable; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 49a3149..6683cdc 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2127,6 +2127,26 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, intel_dp->link_mst = link_mst; } +void intel_dp_set_fia_lane_count(struct intel_dp *intel_dp) +{ + struct drm_device *dev = intel_dp_to_dev(intel_dp); + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + enum tc_port tc_port = intel_port_to_tc(dev_priv, + intel_dig_port->base.port); + u8 lane_count = intel_dp_max_common_lane_count(intel_dp); + u32 val; + + /* In case of legacy/static DP over Type-C port there is no muxing + * with other controllers so this is set to max lane count. + * In case of Type_C it is set to the DFLEXDPSP.DPX4TXLATC value. + */ + val = I915_READ(PORT_TX_DFLEXDPMLE1); + val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port); + val |= DFLEXDPMLE1_DPMLETC(tc_port, lane_count); + I915_WRITE(PORT_TX_DFLEXDPMLE1, val); +} + static void intel_dp_prepare(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1ad7c11..d98cdb9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1676,6 +1676,7 @@ bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, uint8_t lane_count, bool link_mst); +void intel_dp_set_fia_lane_count(struct intel_dp *intel_dp); int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, int link_rate, uint8_t lane_count); void intel_dp_start_link_train(struct intel_dp *intel_dp);