From patchwork Tue Aug 7 23:05:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10559321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F1CF915A6 for ; Tue, 7 Aug 2018 23:10:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E129C29F7F for ; Tue, 7 Aug 2018 23:10:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D53DB29F8C; Tue, 7 Aug 2018 23:10:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 799B029F7F for ; Tue, 7 Aug 2018 23:10:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C7BB6E46D; Tue, 7 Aug 2018 23:10:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4CD576E46A for ; Tue, 7 Aug 2018 23:10:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2018 16:10:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,456,1526367600"; d="scan'208";a="64335756" Received: from anusha-dev.jf.intel.com ([10.7.198.63]) by orsmga006.jf.intel.com with ESMTP; 07 Aug 2018 16:10:04 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Aug 2018 16:05:29 -0700 Message-Id: <1533683132-21625-3-git-send-email-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533683132-21625-1-git-send-email-anusha.srivatsa@intel.com> References: <1533683132-21625-1-git-send-email-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [PATCH 2/5] i915/dp/fec: Check for FEC Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: "Srivatsa, Anusha" For DP 1.4 and above, Display Stream compression can be enabled only if Forward Error Correctin can be performed. If FEC support exists, write to the FEC_READY bit in the FEC_CONFIGURATION DPCD register. v2: Mention External DP where ever FEC is mentioned in the code.Check return status of dpcd reads. (Gaurav) - Do regular mode check even if FEC is not supported. (manasi) v3: Do not perform any dpcd writes in the atomic check phase. (DK, Manasi) v4: Use debug level logging for scenario where sink does not support a feature. (DK) Cc: Gaurav K Singh Cc: Ville Syrjala Cc: Jani Nikula Cc: Manasi Navare Cc: Dhinakaran Pandiyan Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1a8329c..cb8b63e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -652,7 +652,7 @@ intel_dp_mode_valid(struct drm_connector *connector, dsc_max_output_bpp = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; dsc_slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, true); - } else { + } else if (drm_dp_sink_supports_fec(&intel_dp->aux)) { dsc_max_output_bpp = intel_dp_dsc_get_output_bpp(max_link_clock, max_lanes, target_clock, @@ -660,7 +660,8 @@ intel_dp_mode_valid(struct drm_connector *connector, dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, mode->hdisplay); - } + } else + DRM_DEBUG_KMS("Sink device does not Support FEC\n"); } if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || @@ -2000,6 +2001,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp)) return false; + /* DSC not supported if external DP sink does not support FEC */ + if (!intel_dp_is_edp(intel_dp) && + !drm_dp_sink_supports_fec(&intel_dp->aux)) { + DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n"); + return false; + } + /* DSC not supported for DSC sink BPC < 8 */ if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) { DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");