From patchwork Wed Aug 8 12:15:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chauhan, Madhav" X-Patchwork-Id: 10559901 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C211E13AC for ; Wed, 8 Aug 2018 12:26:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B00D12AAA7 for ; Wed, 8 Aug 2018 12:26:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A46492AAB7; Wed, 8 Aug 2018 12:26:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5E0782AAA7 for ; Wed, 8 Aug 2018 12:26:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB3346E557; Wed, 8 Aug 2018 12:26:27 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 556036E54E for ; Wed, 8 Aug 2018 12:26:23 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2018 05:26:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,457,1526367600"; d="scan'208";a="63520860" Received: from madhav-desktop.iind.intel.com ([10.223.25.13]) by orsmga008.jf.intel.com with ESMTP; 08 Aug 2018 05:26:12 -0700 From: Madhav Chauhan To: intel-gfx@lists.freedesktop.org Date: Wed, 8 Aug 2018 17:45:56 +0530 Message-Id: <1533730559-461-10-git-send-email-madhav.chauhan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533730559-461-1-git-send-email-madhav.chauhan@intel.com> References: <1533730559-461-1-git-send-email-madhav.chauhan@intel.com> Subject: [Intel-gfx] [PATCH 09/12] drm/i915/icl: DSI TE interrupt handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, vandita.kulkarni@intel.com, rodrigo.vivi@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When DSI is operating in command mode, timing information is given by the panel using TE signal. TE signals are received as an interrupt. This patch adds the handler for TE interrupts. Signed-off-by: Madhav Chauhan --- drivers/gpu/drm/i915/i915_irq.c | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index a24c670..8ca2396 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1861,6 +1861,45 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) intel_guc_to_host_event_handler(&dev_priv->guc); } +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, + u32 iir_value) +{ + enum pipe pipe = INVALID_PIPE; + enum port port; + enum transcoder tc; + u32 val; + + port = (iir_value & ICL_DSI0_TE) ? PORT_A : PORT_B; + tc = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; + + /* Check if DSI configured in command mode */ + val = I915_READ(DSI_TRANS_FUNC_CONF(tc)); + val = (val & OP_MODE_MASK) >> 28; + + if (val != CMD_MODE_TE_GATE) { + DRM_ERROR("DSI trancoder not configured in command mode\n"); + return; + } + + /* Get PIPE for handling VBLANK event */ + val = I915_READ(TRANS_DDI_FUNC_CTL(tc)); + switch (val & TRANS_DDI_EDP_INPUT_MASK) { + case TRANS_DDI_EDP_INPUT_A_ON: + pipe = PIPE_A; + break; + case TRANS_DDI_EDP_INPUT_B_ONOFF: + pipe = PIPE_B; + break; + case TRANS_DDI_EDP_INPUT_C_ONOFF: + pipe = PIPE_C; + break; + default: + DRM_ERROR("Invalid PIPE\n"); + } + + drm_handle_vblank(&dev_priv->drm, pipe); +} + static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) { enum pipe pipe; @@ -2815,6 +2854,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) found = true; } + if (IS_ICELAKE(dev_priv) && + (iir & (ICL_DSI0_TE | ICL_DSI1_TE))) + gen11_dsi_te_interrupt_handler(dev_priv, iir); + if (!found) DRM_ERROR("Unexpected DE Port interrupt\n"); }