From patchwork Wed Aug 8 12:15:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chauhan, Madhav" X-Patchwork-Id: 10559903 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 16B4A90E3 for ; Wed, 8 Aug 2018 12:26:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0655C2AAA7 for ; Wed, 8 Aug 2018 12:26:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF3962AABC; Wed, 8 Aug 2018 12:26:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A1E292AAA7 for ; Wed, 8 Aug 2018 12:26:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ED9F66E55D; Wed, 8 Aug 2018 12:26:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7B3806E543 for ; Wed, 8 Aug 2018 12:26:23 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2018 05:26:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,457,1526367600"; d="scan'208";a="63520862" Received: from madhav-desktop.iind.intel.com ([10.223.25.13]) by orsmga008.jf.intel.com with ESMTP; 08 Aug 2018 05:26:14 -0700 From: Madhav Chauhan To: intel-gfx@lists.freedesktop.org Date: Wed, 8 Aug 2018 17:45:57 +0530 Message-Id: <1533730559-461-11-git-send-email-madhav.chauhan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533730559-461-1-git-send-email-madhav.chauhan@intel.com> References: <1533730559-461-1-git-send-email-madhav.chauhan@intel.com> Subject: [Intel-gfx] [PATCH 10/12] drm/i915/icl: Unmask/Clear DSI TE interrupts X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, vandita.kulkarni@intel.com, rodrigo.vivi@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP While enabling DSI transcoder, TE interrupts need to be unmasked also they need to be cleared when TE interrupts are received. This patch does same by programming DSI interrupt specific registers. Signed-off-by: Madhav Chauhan --- drivers/gpu/drm/i915/i915_irq.c | 2 ++ drivers/gpu/drm/i915/icl_dsi.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8ca2396..b1e836a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1897,6 +1897,8 @@ void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, DRM_ERROR("Invalid PIPE\n"); } + //TODO: Clear DSI interrupt here + drm_handle_vblank(&dev_priv->drm, pipe); } diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 0ae62a1..bd3cdde 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -66,6 +66,7 @@ void gen11_dsi_configure_te_interrupt(struct intel_encoder *encoder, } } + static void wait_for_dsi_hdr_credit_release(struct intel_dsi *intel_dsi, enum transcoder dsi_trans) { @@ -96,6 +97,26 @@ static enum transcoder dsi_port_to_transcoder(enum port port) return TRANSCODER_DSI_1; } +static void gen11_dsi_clear_te_interrupt(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + u32 tmp; + enum port port; + enum transcoder dsi_trans; + + for_each_dsi_port(port, intel_dsi->ports) { + dsi_trans = dsi_port_to_transcoder(port); + tmp = I915_READ(DSI_INTR_IDENT_REG(dsi_trans)); + if (tmp & TE_EVENT) { + /* TE event received, clear it */ + tmp |= TE_EVENT; + I915_WRITE(DSI_INTR_IDENT_REG(dsi_trans), tmp); + } + } + +} + static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -666,11 +687,24 @@ static void gen11_dsi_configure_transcoder(struct intel_encoder *encoder, tmp &= ~OP_MODE_MASK; tmp |= OP_MODE(CMD_MODE_TE_GATE); tmp |= TE_SOURCE_GPIO; + } I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp); } + if (intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE) { + + /* unmask and clear DSI TE interrupt */ + for_each_dsi_port(port, intel_dsi->ports) { + dsi_trans = dsi_port_to_transcoder(port); + tmp = I915_READ(DSI_INTR_MASK_REG(dsi_trans)); + tmp &= ~TE_EVENT; + I915_WRITE(DSI_INTR_MASK_REG(dsi_trans), tmp); + } + gen11_dsi_clear_te_interrupt(encoder); + } + /* enable port sync mode if dual link */ if (intel_dsi->dual_link) { for_each_dsi_port(port, intel_dsi->ports) {