@@ -3398,10 +3398,18 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_encoder *encoder;
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+ encoder = gen11_dsi_find_cmd_mode_encoder(crtc);
+
+ if (IS_ICELAKE(dev_priv) && encoder)
+ gen11_dsi_configure_te_interrupt(encoder, true);
+ else
+ bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
/* Even if there is no DMC, frame counter can get stuck when
@@ -3452,10 +3460,18 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+ struct intel_encoder *encoder;
unsigned long irqflags;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+ encoder = gen11_dsi_find_cmd_mode_encoder(crtc);
+
+ if (IS_ICELAKE(dev_priv) && encoder)
+ gen11_dsi_configure_te_interrupt(encoder, false);
+ else
+ bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
+
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
If DSI is operating in command mode, then display engine won't be receiving VBLANK interrupt instead of that Tearing Event(TE) interrupt will be received. So in this scenario, we need to enable/disable TE interrupt rather than VBLANK interrupts. Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-)