diff mbox series

[3/4] drm/i915: preparations for enabling P010, P012, P016 formats

Message ID 1534424122-32209-3-git-send-email-juhapekka.heikkila@gmail.com (mailing list archive)
State New, archived
Headers show
Series [1/4] drm: Add P010, P012, P016 format definitions and fourcc | expand

Commit Message

Juha-Pekka Heikkila Aug. 16, 2018, 12:55 p.m. UTC 
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_atomic.c       |  3 +-
 drivers/gpu/drm/i915/intel_atomic_plane.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c      | 46 +++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_drv.h          |  1 +
 drivers/gpu/drm/i915/intel_pm.c           | 19 ++++++-------
 drivers/gpu/drm/i915/intel_sprite.c       | 18 +++++++++++-
 6 files changed, 69 insertions(+), 20 deletions(-)

Comments

Sharma, Swati2 Aug. 21, 2018, 2:26 p.m. UTC | #1 
On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_atomic.c       |  3 +-
>   drivers/gpu/drm/i915/intel_atomic_plane.c |  2 +-
>   drivers/gpu/drm/i915/intel_display.c      | 46 +++++++++++++++++++++++++++----
>   drivers/gpu/drm/i915/intel_drv.h          |  1 +
>   drivers/gpu/drm/i915/intel_pm.c           | 19 ++++++-------
>   drivers/gpu/drm/i915/intel_sprite.c       | 18 +++++++++++-
>   6 files changed, 69 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index b04952b..ab76b72 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>   		/* set scaler mode */
>   		if ((INTEL_GEN(dev_priv) >= 9) &&
>   		    plane_state && plane_state->base.fb &&
> -		    plane_state->base.fb->format->format ==
> -		    DRM_FORMAT_NV12) {
> +		    is_planar_yuv_format(plane_state->base.fb->format->format)) {
>   			if (INTEL_GEN(dev_priv) == 9 &&
>   			    !IS_GEMINILAKE(dev_priv) &&
>   			    !IS_SKYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index dcba645..58b2fc6 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>   	else
>   		crtc_state->active_planes &= ~BIT(intel_plane->id);
>   
> -	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> +	if (state->visible && is_planar_yuv_format(state->fb->format->format))
>   		crtc_state->nv12_planes |= BIT(intel_plane->id);
>   	else
>   		crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 690e1e8..80ce742 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>   		return DRM_FORMAT_RGB565;
>   	case PLANE_CTL_FORMAT_NV12:
>   		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_P010:
> +		return DRM_FORMAT_P010;
> +	case PLANE_CTL_FORMAT_P012:
> +		return DRM_FORMAT_P012;
> +	case PLANE_CTL_FORMAT_P016:
> +		return DRM_FORMAT_P016;
>   	default:
>   	case PLANE_CTL_FORMAT_XRGB_8888:
>   		if (rgb_order) {
> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
>   	 * Handle the AUX surface first since
>   	 * the main surface setup depends on it.
>   	 */
> -	if (fb->format->format == DRM_FORMAT_NV12) {
> +	if (is_planar_yuv_format(fb->format->format)) {
>   		ret = skl_check_nv12_surface(crtc_state, plane_state);
>   		if (ret)
>   			return ret;
> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>   		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>   	case DRM_FORMAT_NV12:
>   		return PLANE_CTL_FORMAT_NV12;
> +	case DRM_FORMAT_P010:
> +		return PLANE_CTL_FORMAT_P010;
> +	case DRM_FORMAT_P012:
> +		return PLANE_CTL_FORMAT_P012;
> +	case DRM_FORMAT_P016:
> +		return PLANE_CTL_FORMAT_P016;
>   	default:
>   		MISSING_CASE(pixel_format);
>   	}
> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>   	need_scaling = src_w != dst_w || src_h != dst_h;
>   
>   	if (plane_scaler_check)
> -		if (pixel_format == DRM_FORMAT_NV12)
> -			need_scaling = true;
> +		need_scaling = is_planar_yuv_format(pixel_format);
>   
>   	if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
>   		need_scaling = true;
> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>   		return 0;
>   	}
>   
> -	if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
> +	if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
>   	    (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
>   		DRM_DEBUG_KMS("NV12: src dimensions not met\n");
>   		return -EINVAL;
> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>   	case DRM_FORMAT_UYVY:
>   	case DRM_FORMAT_VYUY:
>   	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
>   		break;
>   	default:
>   		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
>   	 *            or
>   	 *    cdclk/crtc_clock
>   	 */
> -	mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
> +	mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
>   	tmpclk1 = (1 << 16) * mult - 1;
>   	tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
>   	max_scale = min(tmpclk1, tmpclk2);
> @@ -13411,6 +13425,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>   	case DRM_FORMAT_UYVY:
>   	case DRM_FORMAT_VYUY:
>   	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
>   		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>   			return true;
>   		/* fall through */
> @@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>   			goto err;
>   		}
>   		break;
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
Hi Juha,
Do we need this Y/Yf tiled ccs check here? Its already checked in the 
beginning where its written RC supported only with RGB8888 formats.
> +		if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
> +		    mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
> +			DRM_DEBUG_KMS("RC not to be enabled with %s\n",
> +				      drm_get_format_name(mode_cmd->pixel_format,
> +				      &format_name));
> +			goto err;
> +		}
> +		if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +				      drm_get_format_name(mode_cmd->pixel_format,
> +				      &format_name));
> +			goto err;
> +		}
> +		break;
>   	default:
>   		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>   			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
> @@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>   
>   	drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>   
> -	if (fb->format->format == DRM_FORMAT_NV12 &&
> +	if (is_planar_yuv_format(fb->format->format) &&
>   	    (fb->width < SKL_MIN_YUV_420_SRC_W ||
>   	     fb->height < SKL_MIN_YUV_420_SRC_H ||
>   	     (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7b984ae..20af577 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>   
>   
>   /* intel_sprite.c */
> +bool is_planar_yuv_format(uint32_t pixelformat);
>   int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>   			     int usecs);
>   struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d99e5fa..e1292b2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>   	if (INTEL_GEN(dev_priv) < 11)
>   		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>   
> -	if (fourcc == DRM_FORMAT_NV12) {
> +	if (is_planar_yuv_format(fourcc)) {
>   		skl_ddb_entry_init_from_hw(dev_priv,
>   					   &ddb->plane[pipe][plane_id], val2);
>   		skl_ddb_entry_init_from_hw(dev_priv,
> @@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>   
>   	if (intel_plane->id == PLANE_CURSOR)
>   		return 0;
> -	if (plane == 1 && format != DRM_FORMAT_NV12)
> +	if (plane == 1 && !is_planar_yuv_format(format))
>   		return 0;
>   
>   	/*
> @@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>   	height = drm_rect_height(&intel_pstate->base.src) >> 16;
>   
>   	/* UV plane does 1/2 pixel sub-sampling */
> -	if (plane == 1 && format == DRM_FORMAT_NV12) {
> +	if (plane == 1 && is_planar_yuv_format(format)) {
>   		width /= 2;
>   		height /= 2;
>   	}
> @@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
>   		return 0;
>   
>   	/* For packed formats, and uv-plane, return 0 */
> -	if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
> +	if (plane == 1 && !is_planar_yuv_format(fb->format->format))
>   		return 0;
>   
>   	/* For Non Y-tile return 8-blocks */
> @@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
>   	src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
>   	src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>   
> -	/* Halve UV plane width and height for NV12 */
> +	/* Halve UV plane width and height for NV12 and other planar yuv */
>   	if (plane == 1) {
>   		src_w /= 2;
>   		src_h /= 2;
> @@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>   		return 0;
>   
>   	/* only NV12 format has two planes */
> -	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
> -		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> +	if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
> +		DRM_DEBUG_KMS("Non planar format have single plane\n");
>   		return -EINVAL;
>   	}
>   
> @@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>   	wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
>   	wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>   			 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> -	wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
> +	wp->is_planar = is_planar_yuv_format(fb->format->format);
>   
>   	if (plane->id == PLANE_CURSOR) {
>   		wp->width = intel_pstate->base.crtc_w;
> @@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
>   			return ret;
>   	}
>   
> -	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> -		wm->is_planar = true;
> +	wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
>   
>   	return 0;
>   }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f7026e8..68db026 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -41,6 +41,19 @@
>   #include <drm/i915_drm.h>
>   #include "i915_drv.h"
>   
> +bool is_planar_yuv_format(uint32_t pixelformat)
> +{
> +	switch (pixelformat) {
> +	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
>   int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>   			     int usecs)
>   {
> @@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>   		src->y2 = (src_y + src_h) << 16;
>   
>   		if (fb->format->is_yuv &&
> -    		    fb->format->format != DRM_FORMAT_NV12 &&
> +		    !is_planar_yuv_format(fb->format->format) &&
>   		    (src_x % 2 || src_w % 2)) {
>   			DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
>   				      src_x, src_w);
> @@ -1419,6 +1432,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>   	case DRM_FORMAT_UYVY:
>   	case DRM_FORMAT_VYUY:
>   	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
>   		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>   			return true;
>   		/* fall through */
Juha-Pekka Heikkila Aug. 27, 2018, 10:21 a.m. UTC | #2 
On 21.08.2018 17:26, Sharma, Swati2 wrote:
> On 16-Aug-18 6:25 PM, Juha-Pekka Heikkila wrote:
>> Preparations for enabling P010, P012 and P016 formats. These
>> formats will extend NV12 for larger bit depths.
>>
>> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
>> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_atomic.c       |  3 +-
>>   drivers/gpu/drm/i915/intel_atomic_plane.c |  2 +-
>>   drivers/gpu/drm/i915/intel_display.c      | 46 
>> +++++++++++++++++++++++++++----
>>   drivers/gpu/drm/i915/intel_drv.h          |  1 +
>>   drivers/gpu/drm/i915/intel_pm.c           | 19 ++++++-------
>>   drivers/gpu/drm/i915/intel_sprite.c       | 18 +++++++++++-
>>   6 files changed, 69 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_atomic.c 
>> b/drivers/gpu/drm/i915/intel_atomic.c
>> index b04952b..ab76b72 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic.c
>> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct 
>> drm_i915_private *dev_priv,
>>           /* set scaler mode */
>>           if ((INTEL_GEN(dev_priv) >= 9) &&
>>               plane_state && plane_state->base.fb &&
>> -            plane_state->base.fb->format->format ==
>> -            DRM_FORMAT_NV12) {
>> +            
>> is_planar_yuv_format(plane_state->base.fb->format->format)) {
>>               if (INTEL_GEN(dev_priv) == 9 &&
>>                   !IS_GEMINILAKE(dev_priv) &&
>>                   !IS_SKYLAKE(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c 
>> b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> index dcba645..58b2fc6 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const 
>> struct intel_crtc_state *old_crtc_
>>       else
>>           crtc_state->active_planes &= ~BIT(intel_plane->id);
>> -    if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
>> +    if (state->visible && 
>> is_planar_yuv_format(state->fb->format->format))
>>           crtc_state->nv12_planes |= BIT(intel_plane->id);
>>       else
>>           crtc_state->nv12_planes &= ~BIT(intel_plane->id);
>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 690e1e8..80ce742 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool 
>> rgb_order, bool alpha)
>>           return DRM_FORMAT_RGB565;
>>       case PLANE_CTL_FORMAT_NV12:
>>           return DRM_FORMAT_NV12;
>> +    case PLANE_CTL_FORMAT_P010:
>> +        return DRM_FORMAT_P010;
>> +    case PLANE_CTL_FORMAT_P012:
>> +        return DRM_FORMAT_P012;
>> +    case PLANE_CTL_FORMAT_P016:
>> +        return DRM_FORMAT_P016;
>>       default:
>>       case PLANE_CTL_FORMAT_XRGB_8888:
>>           if (rgb_order) {
>> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct 
>> intel_crtc_state *crtc_state,
>>        * Handle the AUX surface first since
>>        * the main surface setup depends on it.
>>        */
>> -    if (fb->format->format == DRM_FORMAT_NV12) {
>> +    if (is_planar_yuv_format(fb->format->format)) {
>>           ret = skl_check_nv12_surface(crtc_state, plane_state);
>>           if (ret)
>>               return ret;
>> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t 
>> pixel_format)
>>           return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>>       case DRM_FORMAT_NV12:
>>           return PLANE_CTL_FORMAT_NV12;
>> +    case DRM_FORMAT_P010:
>> +        return PLANE_CTL_FORMAT_P010;
>> +    case DRM_FORMAT_P012:
>> +        return PLANE_CTL_FORMAT_P012;
>> +    case DRM_FORMAT_P016:
>> +        return PLANE_CTL_FORMAT_P016;
>>       default:
>>           MISSING_CASE(pixel_format);
>>       }
>> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state 
>> *crtc_state, bool force_detach,
>>       need_scaling = src_w != dst_w || src_h != dst_h;
>>       if (plane_scaler_check)
>> -        if (pixel_format == DRM_FORMAT_NV12)
>> -            need_scaling = true;
>> +        need_scaling = is_planar_yuv_format(pixel_format);
>>       if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
>>           need_scaling = true;
>> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state 
>> *crtc_state, bool force_detach,
>>           return 0;
>>       }
>> -    if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
>> +    if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
>>           (src_h < SKL_MIN_YUV_420_SRC_H || src_w < 
>> SKL_MIN_YUV_420_SRC_W)) {
>>           DRM_DEBUG_KMS("NV12: src dimensions not met\n");
>>           return -EINVAL;
>> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct 
>> intel_crtc_state *crtc_state,
>>       case DRM_FORMAT_UYVY:
>>       case DRM_FORMAT_VYUY:
>>       case DRM_FORMAT_NV12:
>> +    case DRM_FORMAT_P010:
>> +    case DRM_FORMAT_P012:
>> +    case DRM_FORMAT_P016:
>>           break;
>>       default:
>>           DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling 
>> format 0x%x\n",
>> @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
>>        *            or
>>        *    cdclk/crtc_clock
>>        */
>> -    mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
>> +    mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
>>       tmpclk1 = (1 << 16) * mult - 1;
>>       tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
>>       max_scale = min(tmpclk1, tmpclk2);
>> @@ -13411,6 +13425,9 @@ static bool 
>> skl_plane_format_mod_supported(struct drm_plane *_plane,
>>       case DRM_FORMAT_UYVY:
>>       case DRM_FORMAT_VYUY:
>>       case DRM_FORMAT_NV12:
>> +    case DRM_FORMAT_P010:
>> +    case DRM_FORMAT_P012:
>> +    case DRM_FORMAT_P016:
>>           if (modifier == I915_FORMAT_MOD_Yf_TILED)
>>               return true;
>>           /* fall through */
>> @@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct 
>> intel_framebuffer *intel_fb,
>>               goto err;
>>           }
>>           break;
>> +    case DRM_FORMAT_P010:
>> +    case DRM_FORMAT_P012:
>> +    case DRM_FORMAT_P016:
> Hi Juha,
> Do we need this Y/Yf tiled ccs check here? Its already checked in the 
> beginning where its written RC supported only with RGB8888 formats.

You're right. I think underlying code has changed in past months since 
this was written. I'll make another version.

>> +        if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
>> +            mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
>> +            DRM_DEBUG_KMS("RC not to be enabled with %s\n",
>> +                      drm_get_format_name(mode_cmd->pixel_format,
>> +                      &format_name));
>> +            goto err;
>> +        }
>> +        if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
>> +            DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>> +                      drm_get_format_name(mode_cmd->pixel_format,
>> +                      &format_name));
>> +            goto err;
>> +        }
>> +        break;
>>       default:
>>           DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>>                     drm_get_format_name(mode_cmd->pixel_format, 
>> &format_name));
>> @@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct 
>> intel_framebuffer *intel_fb,
>>       drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>> -    if (fb->format->format == DRM_FORMAT_NV12 &&
>> +    if (is_planar_yuv_format(fb->format->format) &&
>>           (fb->width < SKL_MIN_YUV_420_SRC_W ||
>>            fb->height < SKL_MIN_YUV_420_SRC_H ||
>>            (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
>> b/drivers/gpu/drm/i915/intel_drv.h
>> index 7b984ae..20af577 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private 
>> *dev_priv,
>>   /* intel_sprite.c */
>> +bool is_planar_yuv_format(uint32_t pixelformat);
>>   int intel_usecs_to_scanlines(const struct drm_display_mode 
>> *adjusted_mode,
>>                    int usecs);
>>   struct intel_plane *intel_sprite_plane_create(struct 
>> drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index d99e5fa..e1292b2 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct 
>> drm_i915_private *dev_priv,
>>       if (INTEL_GEN(dev_priv) < 11)
>>           val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>> -    if (fourcc == DRM_FORMAT_NV12) {
>> +    if (is_planar_yuv_format(fourcc)) {
>>           skl_ddb_entry_init_from_hw(dev_priv,
>>                          &ddb->plane[pipe][plane_id], val2);
>>           skl_ddb_entry_init_from_hw(dev_priv,
>> @@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct 
>> intel_crtc_state *cstate,
>>       if (intel_plane->id == PLANE_CURSOR)
>>           return 0;
>> -    if (plane == 1 && format != DRM_FORMAT_NV12)
>> +    if (plane == 1 && !is_planar_yuv_format(format))
>>           return 0;
>>       /*
>> @@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct 
>> intel_crtc_state *cstate,
>>       height = drm_rect_height(&intel_pstate->base.src) >> 16;
>>       /* UV plane does 1/2 pixel sub-sampling */
>> -    if (plane == 1 && format == DRM_FORMAT_NV12) {
>> +    if (plane == 1 && is_planar_yuv_format(format)) {
>>           width /= 2;
>>           height /= 2;
>>       }
>> @@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state 
>> *pstate, const int plane)
>>           return 0;
>>       /* For packed formats, and uv-plane, return 0 */
>> -    if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
>> +    if (plane == 1 && !is_planar_yuv_format(fb->format->format))
>>           return 0;
>>       /* For Non Y-tile return 8-blocks */
>> @@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state 
>> *pstate, const int plane)
>>       src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
>>       src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>> -    /* Halve UV plane width and height for NV12 */
>> +    /* Halve UV plane width and height for NV12 and other planar yuv */
>>       if (plane == 1) {
>>           src_w /= 2;
>>           src_h /= 2;
>> @@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct 
>> drm_i915_private *dev_priv,
>>           return 0;
>>       /* only NV12 format has two planes */
>> -    if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
>> -        DRM_DEBUG_KMS("Non NV12 format have single plane\n");
>> +    if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
>> +        DRM_DEBUG_KMS("Non planar format have single plane\n");
>>           return -EINVAL;
>>       }
>> @@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct 
>> drm_i915_private *dev_priv,
>>       wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
>>       wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>>                fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>> -    wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
>> +    wp->is_planar = is_planar_yuv_format(fb->format->format);
>>       if (plane->id == PLANE_CURSOR) {
>>           wp->width = intel_pstate->base.crtc_w;
>> @@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct 
>> drm_i915_private *dev_priv,
>>               return ret;
>>       }
>> -    if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
>> -        wm->is_planar = true;
>> +    wm->is_planar = 
>> is_planar_yuv_format(intel_pstate->base.fb->format->format);
>>       return 0;
>>   }
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
>> b/drivers/gpu/drm/i915/intel_sprite.c
>> index f7026e8..68db026 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -41,6 +41,19 @@
>>   #include <drm/i915_drm.h>
>>   #include "i915_drv.h"
>> +bool is_planar_yuv_format(uint32_t pixelformat)
>> +{
>> +    switch (pixelformat) {
>> +    case DRM_FORMAT_NV12:
>> +    case DRM_FORMAT_P010:
>> +    case DRM_FORMAT_P012:
>> +    case DRM_FORMAT_P016:
>> +        return true;
>> +    default:
>> +        return false;
>> +    }
>> +}
>> +
>>   int intel_usecs_to_scanlines(const struct drm_display_mode 
>> *adjusted_mode,
>>                    int usecs)
>>   {
>> @@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>>           src->y2 = (src_y + src_h) << 16;
>>           if (fb->format->is_yuv &&
>> -                fb->format->format != DRM_FORMAT_NV12 &&
>> +            !is_planar_yuv_format(fb->format->format) &&
>>               (src_x % 2 || src_w % 2)) {
>>               DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 
>> for YUV planes\n",
>>                         src_x, src_w);
>> @@ -1419,6 +1432,9 @@ static bool 
>> skl_plane_format_mod_supported(struct drm_plane *_plane,
>>       case DRM_FORMAT_UYVY:
>>       case DRM_FORMAT_VYUY:
>>       case DRM_FORMAT_NV12:
>> +    case DRM_FORMAT_P010:
>> +    case DRM_FORMAT_P012:
>> +    case DRM_FORMAT_P016:
>>           if (modifier == I915_FORMAT_MOD_Yf_TILED)
>>               return true;
>>           /* fall through */
>
Maarten Lankhorst Aug. 27, 2018, 11:28 a.m. UTC | #3 
Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_atomic.c       |  3 +-
>  drivers/gpu/drm/i915/intel_atomic_plane.c |  2 +-
>  drivers/gpu/drm/i915/intel_display.c      | 46 +++++++++++++++++++++++++++----
>  drivers/gpu/drm/i915/intel_drv.h          |  1 +
>  drivers/gpu/drm/i915/intel_pm.c           | 19 ++++++-------
>  drivers/gpu/drm/i915/intel_sprite.c       | 18 +++++++++++-
>  6 files changed, 69 insertions(+), 20 deletions(-)
For patches 2, 3, 4:

Acked-by: Jani Nikula <jani.nikula@intel.com> #irc, for merging through drm-misc-next.

Are you ok with Swati Sharma's comment on patch 4? I can fix it up when committing.
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index b04952b..ab76b72 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  		/* set scaler mode */
>  		if ((INTEL_GEN(dev_priv) >= 9) &&
>  		    plane_state && plane_state->base.fb &&
> -		    plane_state->base.fb->format->format ==
> -		    DRM_FORMAT_NV12) {
> +		    is_planar_yuv_format(plane_state->base.fb->format->format)) {
>  			if (INTEL_GEN(dev_priv) == 9 &&
>  			    !IS_GEMINILAKE(dev_priv) &&
>  			    !IS_SKYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index dcba645..58b2fc6 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>  	else
>  		crtc_state->active_planes &= ~BIT(intel_plane->id);
>  
> -	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> +	if (state->visible && is_planar_yuv_format(state->fb->format->format))
>  		crtc_state->nv12_planes |= BIT(intel_plane->id);
>  	else
>  		crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 690e1e8..80ce742 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  		return DRM_FORMAT_RGB565;
>  	case PLANE_CTL_FORMAT_NV12:
>  		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_P010:
> +		return DRM_FORMAT_P010;
> +	case PLANE_CTL_FORMAT_P012:
> +		return DRM_FORMAT_P012;
> +	case PLANE_CTL_FORMAT_P016:
> +		return DRM_FORMAT_P016;
>  	default:
>  	case PLANE_CTL_FORMAT_XRGB_8888:
>  		if (rgb_order) {
> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
>  	 * Handle the AUX surface first since
>  	 * the main surface setup depends on it.
>  	 */
> -	if (fb->format->format == DRM_FORMAT_NV12) {
> +	if (is_planar_yuv_format(fb->format->format)) {
>  		ret = skl_check_nv12_surface(crtc_state, plane_state);
>  		if (ret)
>  			return ret;
> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>  		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>  	case DRM_FORMAT_NV12:
>  		return PLANE_CTL_FORMAT_NV12;
> +	case DRM_FORMAT_P010:
> +		return PLANE_CTL_FORMAT_P010;
> +	case DRM_FORMAT_P012:
> +		return PLANE_CTL_FORMAT_P012;
> +	case DRM_FORMAT_P016:
> +		return PLANE_CTL_FORMAT_P016;
>  	default:
>  		MISSING_CASE(pixel_format);
>  	}
> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  	need_scaling = src_w != dst_w || src_h != dst_h;
>  
>  	if (plane_scaler_check)
> -		if (pixel_format == DRM_FORMAT_NV12)
> -			need_scaling = true;
> +		need_scaling = is_planar_yuv_format(pixel_format);
>  
>  	if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
>  		need_scaling = true;
> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  		return 0;
>  	}
>  
> -	if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
> +	if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
>  	    (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
>  		DRM_DEBUG_KMS("NV12: src dimensions not met\n");
>  		return -EINVAL;
> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
>  		break;
>  	default:
>  		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
>  	 *            or
>  	 *    cdclk/crtc_clock
>  	 */
> -	mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
> +	mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
>  	tmpclk1 = (1 << 16) * mult - 1;
>  	tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
>  	max_scale = min(tmpclk1, tmpclk2);
> @@ -13411,6 +13425,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
>  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>  			return true;
>  		/* fall through */
> @@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  			goto err;
>  		}
>  		break;
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
> +		if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
> +		    mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
> +			DRM_DEBUG_KMS("RC not to be enabled with %s\n",
> +				      drm_get_format_name(mode_cmd->pixel_format,
> +				      &format_name));
> +			goto err;
> +		}
> +		if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +				      drm_get_format_name(mode_cmd->pixel_format,
> +				      &format_name));
> +			goto err;
> +		}
> +		break;
>  	default:
>  		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>  			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
> @@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  
>  	drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>  
> -	if (fb->format->format == DRM_FORMAT_NV12 &&
> +	if (is_planar_yuv_format(fb->format->format) &&
>  	    (fb->width < SKL_MIN_YUV_420_SRC_W ||
>  	     fb->height < SKL_MIN_YUV_420_SRC_H ||
>  	     (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 7b984ae..20af577 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>  
>  
>  /* intel_sprite.c */
> +bool is_planar_yuv_format(uint32_t pixelformat);
>  int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>  			     int usecs);
>  struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d99e5fa..e1292b2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>  	if (INTEL_GEN(dev_priv) < 11)
>  		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>  
> -	if (fourcc == DRM_FORMAT_NV12) {
> +	if (is_planar_yuv_format(fourcc)) {
>  		skl_ddb_entry_init_from_hw(dev_priv,
>  					   &ddb->plane[pipe][plane_id], val2);
>  		skl_ddb_entry_init_from_hw(dev_priv,
> @@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>  
>  	if (intel_plane->id == PLANE_CURSOR)
>  		return 0;
> -	if (plane == 1 && format != DRM_FORMAT_NV12)
> +	if (plane == 1 && !is_planar_yuv_format(format))
>  		return 0;
>  
>  	/*
> @@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>  	height = drm_rect_height(&intel_pstate->base.src) >> 16;
>  
>  	/* UV plane does 1/2 pixel sub-sampling */
> -	if (plane == 1 && format == DRM_FORMAT_NV12) {
> +	if (plane == 1 && is_planar_yuv_format(format)) {
>  		width /= 2;
>  		height /= 2;
>  	}
> @@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
>  		return 0;
>  
>  	/* For packed formats, and uv-plane, return 0 */
> -	if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
> +	if (plane == 1 && !is_planar_yuv_format(fb->format->format))
>  		return 0;
>  
>  	/* For Non Y-tile return 8-blocks */
> @@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
>  	src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
>  	src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>  
> -	/* Halve UV plane width and height for NV12 */
> +	/* Halve UV plane width and height for NV12 and other planar yuv */
>  	if (plane == 1) {
>  		src_w /= 2;
>  		src_h /= 2;
> @@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>  		return 0;
>  
>  	/* only NV12 format has two planes */
> -	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
> -		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> +	if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
> +		DRM_DEBUG_KMS("Non planar format have single plane\n");
>  		return -EINVAL;
>  	}
>  
> @@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>  	wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
>  	wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>  			 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> -	wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
> +	wp->is_planar = is_planar_yuv_format(fb->format->format);
>  
>  	if (plane->id == PLANE_CURSOR) {
>  		wp->width = intel_pstate->base.crtc_w;
> @@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
>  			return ret;
>  	}
>  
> -	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> -		wm->is_planar = true;
> +	wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index f7026e8..68db026 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -41,6 +41,19 @@
>  #include <drm/i915_drm.h>
>  #include "i915_drv.h"
>  
> +bool is_planar_yuv_format(uint32_t pixelformat)
> +{
> +	switch (pixelformat) {
> +	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
>  int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>  			     int usecs)
>  {
> @@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>  		src->y2 = (src_y + src_h) << 16;
>  
>  		if (fb->format->is_yuv &&
> -    		    fb->format->format != DRM_FORMAT_NV12 &&
> +		    !is_planar_yuv_format(fb->format->format) &&
>  		    (src_x % 2 || src_w % 2)) {
>  			DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
>  				      src_x, src_w);
> @@ -1419,6 +1432,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_UYVY:
>  	case DRM_FORMAT_VYUY:
>  	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_P010:
> +	case DRM_FORMAT_P012:
> +	case DRM_FORMAT_P016:
>  		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>  			return true;
>  		/* fall through */
Juha-Pekka Heikkila Aug. 27, 2018, 1:09 p.m. UTC | #4 
On 27.08.2018 14:28, Maarten Lankhorst wrote:
> Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
>> Preparations for enabling P010, P012 and P016 formats. These
>> formats will extend NV12 for larger bit depths.
>>
>> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
>> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_atomic.c       |  3 +-
>>   drivers/gpu/drm/i915/intel_atomic_plane.c |  2 +-
>>   drivers/gpu/drm/i915/intel_display.c      | 46 +++++++++++++++++++++++++++----
>>   drivers/gpu/drm/i915/intel_drv.h          |  1 +
>>   drivers/gpu/drm/i915/intel_pm.c           | 19 ++++++-------
>>   drivers/gpu/drm/i915/intel_sprite.c       | 18 +++++++++++-
>>   6 files changed, 69 insertions(+), 20 deletions(-)
> For patches 2, 3, 4:
> 
> Acked-by: Jani Nikula <jani.nikula@intel.com> #irc, for merging through drm-misc-next.
> 
> Are you ok with Swati Sharma's comment on patch 4? I can fix it up when committing.

I'm all ok with Swati Sharma's comment.

/Juha-Pekka

>> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
>> index b04952b..ab76b72 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic.c
>> @@ -334,8 +334,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>>   		/* set scaler mode */
>>   		if ((INTEL_GEN(dev_priv) >= 9) &&
>>   		    plane_state && plane_state->base.fb &&
>> -		    plane_state->base.fb->format->format ==
>> -		    DRM_FORMAT_NV12) {
>> +		    is_planar_yuv_format(plane_state->base.fb->format->format)) {
>>   			if (INTEL_GEN(dev_priv) == 9 &&
>>   			    !IS_GEMINILAKE(dev_priv) &&
>>   			    !IS_SKYLAKE(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> index dcba645..58b2fc6 100644
>> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
>> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
>> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
>>   	else
>>   		crtc_state->active_planes &= ~BIT(intel_plane->id);
>>   
>> -	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
>> +	if (state->visible && is_planar_yuv_format(state->fb->format->format))
>>   		crtc_state->nv12_planes |= BIT(intel_plane->id);
>>   	else
>>   		crtc_state->nv12_planes &= ~BIT(intel_plane->id);
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 690e1e8..80ce742 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>>   		return DRM_FORMAT_RGB565;
>>   	case PLANE_CTL_FORMAT_NV12:
>>   		return DRM_FORMAT_NV12;
>> +	case PLANE_CTL_FORMAT_P010:
>> +		return DRM_FORMAT_P010;
>> +	case PLANE_CTL_FORMAT_P012:
>> +		return DRM_FORMAT_P012;
>> +	case PLANE_CTL_FORMAT_P016:
>> +		return DRM_FORMAT_P016;
>>   	default:
>>   	case PLANE_CTL_FORMAT_XRGB_8888:
>>   		if (rgb_order) {
>> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
>>   	 * Handle the AUX surface first since
>>   	 * the main surface setup depends on it.
>>   	 */
>> -	if (fb->format->format == DRM_FORMAT_NV12) {
>> +	if (is_planar_yuv_format(fb->format->format)) {
>>   		ret = skl_check_nv12_surface(crtc_state, plane_state);
>>   		if (ret)
>>   			return ret;
>> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>>   		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>>   	case DRM_FORMAT_NV12:
>>   		return PLANE_CTL_FORMAT_NV12;
>> +	case DRM_FORMAT_P010:
>> +		return PLANE_CTL_FORMAT_P010;
>> +	case DRM_FORMAT_P012:
>> +		return PLANE_CTL_FORMAT_P012;
>> +	case DRM_FORMAT_P016:
>> +		return PLANE_CTL_FORMAT_P016;
>>   	default:
>>   		MISSING_CASE(pixel_format);
>>   	}
>> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>>   	need_scaling = src_w != dst_w || src_h != dst_h;
>>   
>>   	if (plane_scaler_check)
>> -		if (pixel_format == DRM_FORMAT_NV12)
>> -			need_scaling = true;
>> +		need_scaling = is_planar_yuv_format(pixel_format);
>>   
>>   	if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
>>   		need_scaling = true;
>> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>>   		return 0;
>>   	}
>>   
>> -	if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
>> +	if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
>>   	    (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
>>   		DRM_DEBUG_KMS("NV12: src dimensions not met\n");
>>   		return -EINVAL;
>> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>>   	case DRM_FORMAT_UYVY:
>>   	case DRM_FORMAT_VYUY:
>>   	case DRM_FORMAT_NV12:
>> +	case DRM_FORMAT_P010:
>> +	case DRM_FORMAT_P012:
>> +	case DRM_FORMAT_P016:
>>   		break;
>>   	default:
>>   		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
>> @@ -13179,7 +13193,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
>>   	 *            or
>>   	 *    cdclk/crtc_clock
>>   	 */
>> -	mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
>> +	mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
>>   	tmpclk1 = (1 << 16) * mult - 1;
>>   	tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
>>   	max_scale = min(tmpclk1, tmpclk2);
>> @@ -13411,6 +13425,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>>   	case DRM_FORMAT_UYVY:
>>   	case DRM_FORMAT_VYUY:
>>   	case DRM_FORMAT_NV12:
>> +	case DRM_FORMAT_P010:
>> +	case DRM_FORMAT_P012:
>> +	case DRM_FORMAT_P016:
>>   		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>>   			return true;
>>   		/* fall through */
>> @@ -14556,6 +14573,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>   			goto err;
>>   		}
>>   		break;
>> +	case DRM_FORMAT_P010:
>> +	case DRM_FORMAT_P012:
>> +	case DRM_FORMAT_P016:
>> +		if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
>> +		    mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
>> +			DRM_DEBUG_KMS("RC not to be enabled with %s\n",
>> +				      drm_get_format_name(mode_cmd->pixel_format,
>> +				      &format_name));
>> +			goto err;
>> +		}
>> +		if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
>> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>> +				      drm_get_format_name(mode_cmd->pixel_format,
>> +				      &format_name));
>> +			goto err;
>> +		}
>> +		break;
>>   	default:
>>   		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>>   			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
>> @@ -14568,7 +14602,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>   
>>   	drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>>   
>> -	if (fb->format->format == DRM_FORMAT_NV12 &&
>> +	if (is_planar_yuv_format(fb->format->format) &&
>>   	    (fb->width < SKL_MIN_YUV_420_SRC_W ||
>>   	     fb->height < SKL_MIN_YUV_420_SRC_H ||
>>   	     (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 7b984ae..20af577 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -2097,6 +2097,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>>   
>>   
>>   /* intel_sprite.c */
>> +bool is_planar_yuv_format(uint32_t pixelformat);
>>   int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>>   			     int usecs);
>>   struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index d99e5fa..e1292b2 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3942,7 +3942,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
>>   	if (INTEL_GEN(dev_priv) < 11)
>>   		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>>   
>> -	if (fourcc == DRM_FORMAT_NV12) {
>> +	if (is_planar_yuv_format(fourcc)) {
>>   		skl_ddb_entry_init_from_hw(dev_priv,
>>   					   &ddb->plane[pipe][plane_id], val2);
>>   		skl_ddb_entry_init_from_hw(dev_priv,
>> @@ -4150,7 +4150,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>>   
>>   	if (intel_plane->id == PLANE_CURSOR)
>>   		return 0;
>> -	if (plane == 1 && format != DRM_FORMAT_NV12)
>> +	if (plane == 1 && !is_planar_yuv_format(format))
>>   		return 0;
>>   
>>   	/*
>> @@ -4162,7 +4162,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>>   	height = drm_rect_height(&intel_pstate->base.src) >> 16;
>>   
>>   	/* UV plane does 1/2 pixel sub-sampling */
>> -	if (plane == 1 && format == DRM_FORMAT_NV12) {
>> +	if (plane == 1 && is_planar_yuv_format(format)) {
>>   		width /= 2;
>>   		height /= 2;
>>   	}
>> @@ -4229,7 +4229,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
>>   		return 0;
>>   
>>   	/* For packed formats, and uv-plane, return 0 */
>> -	if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
>> +	if (plane == 1 && !is_planar_yuv_format(fb->format->format))
>>   		return 0;
>>   
>>   	/* For Non Y-tile return 8-blocks */
>> @@ -4247,7 +4247,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
>>   	src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
>>   	src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>>   
>> -	/* Halve UV plane width and height for NV12 */
>> +	/* Halve UV plane width and height for NV12 and other planar yuv */
>>   	if (plane == 1) {
>>   		src_w /= 2;
>>   		src_h /= 2;
>> @@ -4526,8 +4526,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>>   		return 0;
>>   
>>   	/* only NV12 format has two planes */
>> -	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
>> -		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
>> +	if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
>> +		DRM_DEBUG_KMS("Non planar format have single plane\n");
>>   		return -EINVAL;
>>   	}
>>   
>> @@ -4538,7 +4538,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
>>   	wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
>>   	wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
>>   			 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
>> -	wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
>> +	wp->is_planar = is_planar_yuv_format(fb->format->format);
>>   
>>   	if (plane->id == PLANE_CURSOR) {
>>   		wp->width = intel_pstate->base.crtc_w;
>> @@ -4813,8 +4813,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
>>   			return ret;
>>   	}
>>   
>> -	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
>> -		wm->is_planar = true;
>> +	wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
>>   
>>   	return 0;
>>   }
>> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
>> index f7026e8..68db026 100644
>> --- a/drivers/gpu/drm/i915/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/intel_sprite.c
>> @@ -41,6 +41,19 @@
>>   #include <drm/i915_drm.h>
>>   #include "i915_drv.h"
>>   
>> +bool is_planar_yuv_format(uint32_t pixelformat)
>> +{
>> +	switch (pixelformat) {
>> +	case DRM_FORMAT_NV12:
>> +	case DRM_FORMAT_P010:
>> +	case DRM_FORMAT_P012:
>> +	case DRM_FORMAT_P016:
>> +		return true;
>> +	default:
>> +		return false;
>> +	}
>> +}
>> +
>>   int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
>>   			     int usecs)
>>   {
>> @@ -1039,7 +1052,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
>>   		src->y2 = (src_y + src_h) << 16;
>>   
>>   		if (fb->format->is_yuv &&
>> -    		    fb->format->format != DRM_FORMAT_NV12 &&
>> +		    !is_planar_yuv_format(fb->format->format) &&
>>   		    (src_x % 2 || src_w % 2)) {
>>   			DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
>>   				      src_x, src_w);
>> @@ -1419,6 +1432,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>>   	case DRM_FORMAT_UYVY:
>>   	case DRM_FORMAT_VYUY:
>>   	case DRM_FORMAT_NV12:
>> +	case DRM_FORMAT_P010:
>> +	case DRM_FORMAT_P012:
>> +	case DRM_FORMAT_P016:
>>   		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>>   			return true;
>>   		/* fall through */
> 
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index b04952b..ab76b72 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -334,8 +334,7 @@  int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 		/* set scaler mode */
 		if ((INTEL_GEN(dev_priv) >= 9) &&
 		    plane_state && plane_state->base.fb &&
-		    plane_state->base.fb->format->format ==
-		    DRM_FORMAT_NV12) {
+		    is_planar_yuv_format(plane_state->base.fb->format->format)) {
 			if (INTEL_GEN(dev_priv) == 9 &&
 			    !IS_GEMINILAKE(dev_priv) &&
 			    !IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index dcba645..58b2fc6 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -182,7 +182,7 @@  int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
 	else
 		crtc_state->active_planes &= ~BIT(intel_plane->id);
 
-	if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+	if (state->visible && is_planar_yuv_format(state->fb->format->format))
 		crtc_state->nv12_planes |= BIT(intel_plane->id);
 	else
 		crtc_state->nv12_planes &= ~BIT(intel_plane->id);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 690e1e8..80ce742 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2667,6 +2667,12 @@  int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 		return DRM_FORMAT_RGB565;
 	case PLANE_CTL_FORMAT_NV12:
 		return DRM_FORMAT_NV12;
+	case PLANE_CTL_FORMAT_P010:
+		return DRM_FORMAT_P010;
+	case PLANE_CTL_FORMAT_P012:
+		return DRM_FORMAT_P012;
+	case PLANE_CTL_FORMAT_P016:
+		return DRM_FORMAT_P016;
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
@@ -3182,7 +3188,7 @@  int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
 	 * Handle the AUX surface first since
 	 * the main surface setup depends on it.
 	 */
-	if (fb->format->format == DRM_FORMAT_NV12) {
+	if (is_planar_yuv_format(fb->format->format)) {
 		ret = skl_check_nv12_surface(crtc_state, plane_state);
 		if (ret)
 			return ret;
@@ -3507,6 +3513,12 @@  static u32 skl_plane_ctl_format(uint32_t pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 	case DRM_FORMAT_NV12:
 		return PLANE_CTL_FORMAT_NV12;
+	case DRM_FORMAT_P010:
+		return PLANE_CTL_FORMAT_P010;
+	case DRM_FORMAT_P012:
+		return PLANE_CTL_FORMAT_P012;
+	case DRM_FORMAT_P016:
+		return PLANE_CTL_FORMAT_P016;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -4808,8 +4820,7 @@  skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	need_scaling = src_w != dst_w || src_h != dst_h;
 
 	if (plane_scaler_check)
-		if (pixel_format == DRM_FORMAT_NV12)
-			need_scaling = true;
+		need_scaling = is_planar_yuv_format(pixel_format);
 
 	if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
 		need_scaling = true;
@@ -4850,7 +4861,7 @@  skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		return 0;
 	}
 
-	if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
+	if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
 	    (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
 		DRM_DEBUG_KMS("NV12: src dimensions not met\n");
 		return -EINVAL;
@@ -4955,6 +4966,9 @@  static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_P010:
+	case DRM_FORMAT_P012:
+	case DRM_FORMAT_P016:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -13179,7 +13193,7 @@  skl_max_scale(struct intel_crtc *intel_crtc,
 	 *            or
 	 *    cdclk/crtc_clock
 	 */
-	mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+	mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
 	tmpclk1 = (1 << 16) * mult - 1;
 	tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
 	max_scale = min(tmpclk1, tmpclk2);
@@ -13411,6 +13425,9 @@  static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_P010:
+	case DRM_FORMAT_P012:
+	case DRM_FORMAT_P016:
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
 		/* fall through */
@@ -14556,6 +14573,23 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 		break;
+	case DRM_FORMAT_P010:
+	case DRM_FORMAT_P012:
+	case DRM_FORMAT_P016:
+		if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
+		    mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
+			DRM_DEBUG_KMS("RC not to be enabled with %s\n",
+				      drm_get_format_name(mode_cmd->pixel_format,
+				      &format_name));
+			goto err;
+		}
+		if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
+			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+				      drm_get_format_name(mode_cmd->pixel_format,
+				      &format_name));
+			goto err;
+		}
+		break;
 	default:
 		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
@@ -14568,7 +14602,7 @@  static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 
 	drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
 
-	if (fb->format->format == DRM_FORMAT_NV12 &&
+	if (is_planar_yuv_format(fb->format->format) &&
 	    (fb->width < SKL_MIN_YUV_420_SRC_W ||
 	     fb->height < SKL_MIN_YUV_420_SRC_H ||
 	     (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b984ae..20af577 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2097,6 +2097,7 @@  bool intel_sdvo_init(struct drm_i915_private *dev_priv,
 
 
 /* intel_sprite.c */
+bool is_planar_yuv_format(uint32_t pixelformat);
 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
 			     int usecs);
 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d99e5fa..e1292b2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3942,7 +3942,7 @@  skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 	if (INTEL_GEN(dev_priv) < 11)
 		val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
 
-	if (fourcc == DRM_FORMAT_NV12) {
+	if (is_planar_yuv_format(fourcc)) {
 		skl_ddb_entry_init_from_hw(dev_priv,
 					   &ddb->plane[pipe][plane_id], val2);
 		skl_ddb_entry_init_from_hw(dev_priv,
@@ -4150,7 +4150,7 @@  skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 
 	if (intel_plane->id == PLANE_CURSOR)
 		return 0;
-	if (plane == 1 && format != DRM_FORMAT_NV12)
+	if (plane == 1 && !is_planar_yuv_format(format))
 		return 0;
 
 	/*
@@ -4162,7 +4162,7 @@  skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 	height = drm_rect_height(&intel_pstate->base.src) >> 16;
 
 	/* UV plane does 1/2 pixel sub-sampling */
-	if (plane == 1 && format == DRM_FORMAT_NV12) {
+	if (plane == 1 && is_planar_yuv_format(format)) {
 		width /= 2;
 		height /= 2;
 	}
@@ -4229,7 +4229,7 @@  skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
 		return 0;
 
 	/* For packed formats, and uv-plane, return 0 */
-	if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
+	if (plane == 1 && !is_planar_yuv_format(fb->format->format))
 		return 0;
 
 	/* For Non Y-tile return 8-blocks */
@@ -4247,7 +4247,7 @@  skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
 	src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
 	src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
 
-	/* Halve UV plane width and height for NV12 */
+	/* Halve UV plane width and height for NV12 and other planar yuv */
 	if (plane == 1) {
 		src_w /= 2;
 		src_h /= 2;
@@ -4526,8 +4526,8 @@  skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		return 0;
 
 	/* only NV12 format has two planes */
-	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
-		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+	if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
+		DRM_DEBUG_KMS("Non planar format have single plane\n");
 		return -EINVAL;
 	}
 
@@ -4538,7 +4538,7 @@  skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 	wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
 	wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 			 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-	wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
+	wp->is_planar = is_planar_yuv_format(fb->format->format);
 
 	if (plane->id == PLANE_CURSOR) {
 		wp->width = intel_pstate->base.crtc_w;
@@ -4813,8 +4813,7 @@  skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 			return ret;
 	}
 
-	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
-		wm->is_planar = true;
+	wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f7026e8..68db026 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,6 +41,19 @@ 
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 
+bool is_planar_yuv_format(uint32_t pixelformat)
+{
+	switch (pixelformat) {
+	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_P010:
+	case DRM_FORMAT_P012:
+	case DRM_FORMAT_P016:
+		return true;
+	default:
+		return false;
+	}
+}
+
 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
 			     int usecs)
 {
@@ -1039,7 +1052,7 @@  intel_check_sprite_plane(struct intel_plane *plane,
 		src->y2 = (src_y + src_h) << 16;
 
 		if (fb->format->is_yuv &&
-    		    fb->format->format != DRM_FORMAT_NV12 &&
+		    !is_planar_yuv_format(fb->format->format) &&
 		    (src_x % 2 || src_w % 2)) {
 			DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
 				      src_x, src_w);
@@ -1419,6 +1432,9 @@  static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_P010:
+	case DRM_FORMAT_P012:
+	case DRM_FORMAT_P016:
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
 		/* fall through */