From patchwork Fri Sep 14 06:54:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 10600493 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 25995933 for ; Fri, 14 Sep 2018 09:12:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 02F312B124 for ; Fri, 14 Sep 2018 09:12:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E90B52B130; Fri, 14 Sep 2018 09:12:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8D60B2B124 for ; Fri, 14 Sep 2018 09:12:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C5C3F6E753; Fri, 14 Sep 2018 09:10:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 021556E008 for ; Fri, 14 Sep 2018 07:07:55 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Sep 2018 00:07:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,372,1531810800"; d="scan'208";a="83443481" Received: from vandita-desktop.iind.intel.com ([10.223.25.24]) by orsmga003.jf.intel.com with ESMTP; 14 Sep 2018 00:07:41 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Sep 2018 12:24:12 +0530 Message-Id: <1536908054-2176-2-git-send-email-vandita.kulkarni@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536908054-2176-1-git-send-email-vandita.kulkarni@intel.com> References: <1536908054-2176-1-git-send-email-vandita.kulkarni@intel.com> Subject: [Intel-gfx] [RFC 1/3] drm/i915/icl: Restructure ICL DPLL enable functionality X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, paulo.r.zanoni@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Madhav Chauhan In Gen11, DPLL 0 and 1 are shared between DDI and DSI. Most of the steps for enabling DPLL are common across DDI and DSI. This patch makes icl_dpll_enable() generic which will be used by all the encoders. Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/intel_ddi.c | 12 ++++++++++++ drivers/gpu/drm/i915/intel_dpll_mgr.c | 19 ++----------------- drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 +- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index cd01a09..2942a24 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2810,6 +2810,18 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, mutex_lock(&dev_priv->dpll_lock); if (IS_ICELAKE(dev_priv)) { + enum intel_dpll_id id = pll->info->id; + i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id); + + val = I915_READ(enable_reg); + val |= PLL_ENABLE; + I915_WRITE(enable_reg, val); + + /* TODO: wait times missing from the spec. */ + if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, + PLL_LOCK, 5)) + DRM_ERROR("PLL %d not locked\n", id); + if (port >= PORT_C) I915_WRITE(DDI_CLK_SEL(port), icl_pll_to_ddi_pll_sel(encoder, pll)); diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index e6cac92..36ed155 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2930,7 +2930,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, return pll; } -static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id) +i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id) { switch (id) { default: @@ -3119,22 +3119,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, default: MISSING_CASE(id); } - - /* - * DVFS pre sequence would be here, but in our driver the cdclk code - * paths should already be setting the appropriate voltage, hence we do - * nothign here. - */ - - val = I915_READ(enable_reg); - val |= PLL_ENABLE; - I915_WRITE(enable_reg, val); - - if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK, - 1)) /* 600us actually. */ - DRM_ERROR("PLL %d not locked\n", id); - - /* DVFS post sequence would be here. See the comment above. */ + /* Encoder specific PLL enable steps are added in encoder file */ } static void icl_pll_disable(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h index bf0de8a..9e89265 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h @@ -345,5 +345,5 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv, uint32_t pll_id); int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv); - +i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id); #endif /* _INTEL_DPLL_MGR_H_ */