From patchwork Fri Sep 14 06:54:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 10600503 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CB2C112B for ; Fri, 14 Sep 2018 09:16:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0BB992A45B for ; Fri, 14 Sep 2018 09:16:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F3C182B3EC; Fri, 14 Sep 2018 09:16:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A600B2A45B for ; Fri, 14 Sep 2018 09:16:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 75DAF6E821; Fri, 14 Sep 2018 09:10:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 83E276E008 for ; Fri, 14 Sep 2018 07:08:07 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Sep 2018 00:08:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,372,1531810800"; d="scan'208";a="83443507" Received: from vandita-desktop.iind.intel.com ([10.223.25.24]) by orsmga003.jf.intel.com with ESMTP; 14 Sep 2018 00:07:43 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Sep 2018 12:24:13 +0530 Message-Id: <1536908054-2176-3-git-send-email-vandita.kulkarni@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1536908054-2176-1-git-send-email-vandita.kulkarni@intel.com> References: <1536908054-2176-1-git-send-email-vandita.kulkarni@intel.com> Subject: [Intel-gfx] [RFC 2/3] drm/i915/icl: Enable Gen11 DSI PLL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, paulo.r.zanoni@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Madhav Chauhan This patch implements steps specific to DSI for enabling PLL. Signed-off-by: Madhav Chauhan Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/icl_dsi.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 13830e4..c530e25 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -54,6 +54,45 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder) } } +static void gen11_dsi_pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config) +{ + struct drm_crtc *crtc = pipe_config->base.crtc; + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_shared_dpll *pll = intel_crtc->config->shared_dpll; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + enum intel_dpll_id id = pll->info->id; + i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id); + enum port port; + uint32_t val; + + /** + * Note: Following PLL enable steps are specific to DSI, + * some common steps for all encoder will be done by dpll_enable(). + */ + + mutex_lock(&dev_priv->dpll_lock); + + for_each_dsi_port(port, intel_dsi->ports) { + val = I915_READ(DPCLKA_CFGCR0_ICL); + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); + val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); + I915_WRITE(DPCLKA_CFGCR0_ICL, val); + POSTING_READ(DPCLKA_CFGCR0_ICL); + } + + mutex_unlock(&dev_priv->dpll_lock); + + gen11_dsi_program_esc_clk_div(encoder); + val = I915_READ(enable_reg); + val |= PLL_ENABLE; + I915_WRITE(enable_reg, val); + + if (wait_for_us((I915_READ(enable_reg) & PLL_LOCK), 600)) + DRM_ERROR("PLL %d not locked\n", id); +} + static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -120,7 +159,7 @@ static void __attribute__((unused)) gen11_dsi_enable_io_power(encoder); /* step3: enable DSI PLL */ - gen11_dsi_program_esc_clk_div(encoder); + gen11_dsi_pll_enable(encoder, pipe_config); /* step4: enable DSI port and DPHY */ gen11_dsi_enable_port_and_phy(encoder);