From patchwork Fri Sep 21 09:13:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kedar J. Karanje" X-Patchwork-Id: 10609557 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5268A112B for ; Fri, 21 Sep 2018 09:55:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 412152DCF5 for ; Fri, 21 Sep 2018 09:55:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 35B922DD07; Fri, 21 Sep 2018 09:55:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D01D22DCF5 for ; Fri, 21 Sep 2018 09:55:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F4EB6E753; Fri, 21 Sep 2018 09:55:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4AC6E6E73B for ; Fri, 21 Sep 2018 09:55:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2018 02:55:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,284,1534834800"; d="scan'208";a="82212568" Received: from kedar-linux-box.iind.intel.com ([10.66.254.48]) by FMSMGA003.fm.intel.com with ESMTP; 21 Sep 2018 02:55:46 -0700 From: kedar.j.karanje@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Sep 2018 14:43:50 +0530 Message-Id: <1537521230-22904-5-git-send-email-kedar.j.karanje@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> References: <1537521230-22904-1-git-send-email-kedar.j.karanje@intel.com> Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Predictive governor to control eu/slice/subslice based on workload X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Praveen Diwakar , Yogesh Marathe , Ankit Navik , Aravindan Muthukumar MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Praveen Diwakar High resoluton timer is used for this purpose. Debugfs is provided to enable/disable/update timer configuration Change-Id: I35d692c5afe962fcad4573185bc6f744487711d0 Signed-off-by: Praveen Diwakar Signed-off-by: Yogesh Marathe Signed-off-by: Aravindan Muthukumar Signed-off-by: Kedar J Karanje Signed-off-by: Ankit Navik --- drivers/gpu/drm/i915/i915_debugfs.c | 94 ++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f9ce35d..81ba509 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4740,6 +4740,97 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_drrs_status", i915_drrs_status, 0}, {"i915_rps_boost_info", i915_rps_boost_info, 0}, }; + +#define POLL_PERIOD_MS (1000 * 1000) +#define PENDING_REQ_0 0 /* No active request pending*/ +#define PENDING_REQ_3 3 /* Threshold value of 3 active request pending*/ + /* Anything above this is considered as HIGH load + * context + */ + /* And less is considered as LOW load*/ + /* And equal is considered as mediaum load */ + +static int predictive_load_enable; +static int predictive_load_timer_init; + +static enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer) +{ + struct drm_i915_private *dev_priv = + container_of(hrtimer, typeof(*dev_priv), + pred_timer); + enum intel_engine_id id; + struct intel_engine_cs *engine; + struct i915_gem_context *ctx; + u64 req_pending; + + list_for_each_entry(ctx, &dev_priv->contexts.list, link) { + + if (!ctx->name) + continue; + + mutex_lock(&dev_priv->pred_mutex); + req_pending = ctx->req_cnt; + mutex_unlock(&dev_priv->pred_mutex); + + if (req_pending == PENDING_REQ_0) + continue; + + if (req_pending > PENDING_REQ_3) + ctx->load_type = LOAD_TYPE_HIGH; + else if (req_pending == PENDING_REQ_3) + ctx->load_type = LOAD_TYPE_MEDIUM; + else if (req_pending < PENDING_REQ_3) + ctx->load_type = LOAD_TYPE_LOW; + + i915_set_optimum_config(ctx->load_type, ctx, KABYLAKE_GT3); + } + + hrtimer_forward_now(hrtimer, + ns_to_ktime(predictive_load_enable*POLL_PERIOD_MS)); + + return HRTIMER_RESTART; +} + +static int +i915_predictive_load_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + *val = predictive_load_enable; + return 0; +} + +static int +i915_predictive_load_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + struct intel_device_info *info; + + info = mkwrite_device_info(dev_priv); + + predictive_load_enable = val; + + if (predictive_load_enable) { + if (!predictive_load_timer_init) { + hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + dev_priv->pred_timer.function = predictive_load_cb; + predictive_load_timer_init = 1; + } + hrtimer_start(&dev_priv->pred_timer, + ns_to_ktime(predictive_load_enable*POLL_PERIOD_MS), + HRTIMER_MODE_REL_PINNED); + } else { + hrtimer_cancel(&dev_priv->pred_timer); + } + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_predictive_load_ctl, + i915_predictive_load_get, i915_predictive_load_set, + "%llu\n"); + #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) static const struct i915_debugfs_files { @@ -4769,7 +4860,8 @@ static const struct i915_debugfs_files { {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, {"i915_ipc_status", &i915_ipc_status_fops}, {"i915_drrs_ctl", &i915_drrs_ctl_fops}, - {"i915_edp_psr_debug", &i915_edp_psr_debug_fops} + {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}, + {"i915_predictive_load_ctl", &i915_predictive_load_ctl} }; int i915_debugfs_register(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 137ec33..0505c47 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1552,6 +1552,7 @@ struct intel_cdclk_state { }; struct drm_i915_private { + struct hrtimer pred_timer; struct drm_device drm; struct kmem_cache *objects;