From patchwork Thu Sep 27 16:37:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaolin Zhang X-Patchwork-Id: 10617419 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 31168112B for ; Thu, 27 Sep 2018 07:00:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F43E2B07E for ; Thu, 27 Sep 2018 07:00:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 111AE2B083; Thu, 27 Sep 2018 07:00:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=2.0 tests=BAYES_00,DATE_IN_FUTURE_06_12, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A5F982B07E for ; Thu, 27 Sep 2018 07:00:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 63B0D6E543; Thu, 27 Sep 2018 06:58:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 554196E524; Thu, 27 Sep 2018 06:58:44 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Sep 2018 23:58:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,309,1534834800"; d="scan'208";a="266124225" Received: from vca-bj120.bj.intel.com ([10.240.192.120]) by fmsmga005.fm.intel.com with ESMTP; 26 Sep 2018 23:57:49 -0700 From: Xiaolin Zhang To: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Thu, 27 Sep 2018 12:37:48 -0400 Message-Id: <1538066275-52932-4-git-send-email-xiaolin.zhang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1538066275-52932-1-git-send-email-xiaolin.zhang@intel.com> References: <1538066275-52932-1-git-send-email-xiaolin.zhang@intel.com> Subject: [Intel-gfx] [RFC 03/10] drm/i915/gvt: context submission pvmmio optimization X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhenyu.z.wang@intel.com, hang.yuan@intel.com, joonas.lahtinen@intel.com, fei.jiang@intel.com, zhiyuan.lv@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP It is performance optimization to reduce mmio trap numbers from 4 to 1 durning ELSP porting writing (context submission). When context subission, to cache elsp_data[4] values in the shared page, the last elsp_data[0] port writing will be trapped to gvt for real context submission. Use PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 37 ++++++++++++++++++++++++++++++++++++- 2 files changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 0f6a38b..6c81c87 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -69,7 +69,7 @@ param(bool, enable_dp_mst, true) \ param(bool, enable_dpcd_backlight, false) \ param(bool, enable_gvt, false) \ - param(int, enable_pvmmio, 0) + param(int, enable_pvmmio, PVMMIO_ELSP_SUBMIT) #define MEMBER(T, member, ...) T member; struct i915_params { diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4b28225..cdc713c 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -451,7 +451,12 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) { struct intel_engine_execlists *execlists = &engine->execlists; struct execlist_port *port = execlists->port; + u32 __iomem *elsp = + engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); + u32 *elsp_data; unsigned int n; + u32 descs[4]; + int i = 0; /* * We can skip acquiring intel_runtime_pm_get() here as it was taken @@ -494,8 +499,24 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) GEM_BUG_ON(!n); desc = 0; } + if (PVMMIO_LEVEL_ENABLE(engine->i915, PVMMIO_ELSP_SUBMIT)) { + GEM_BUG_ON(i >= 4); + descs[i] = upper_32_bits(desc); + descs[i + 1] = lower_32_bits(desc); + i += 2; + } else { + write_desc(execlists, desc, n); + } + } - write_desc(execlists, desc, n); + if (PVMMIO_LEVEL_ENABLE(engine->i915, PVMMIO_ELSP_SUBMIT)) { + spin_lock(&engine->i915->shared_page_lock); + elsp_data = engine->i915->shared_page->elsp_data; + *elsp_data = descs[0]; + *(elsp_data + 1) = descs[1]; + *(elsp_data + 2) = descs[2]; + writel(descs[3], elsp); + spin_unlock(&engine->i915->shared_page_lock); } /* we need to manually load the submit queue */ @@ -538,11 +559,25 @@ static void inject_preempt_context(struct intel_engine_cs *engine) struct intel_engine_execlists *execlists = &engine->execlists; struct intel_context *ce = to_intel_context(engine->i915->preempt_context, engine); + u32 __iomem *elsp = + engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); + u32 *elsp_data; unsigned int n; GEM_BUG_ON(execlists->preempt_complete_status != upper_32_bits(ce->lrc_desc)); + if (PVMMIO_LEVEL_ENABLE(engine->i915, PVMMIO_ELSP_SUBMIT)) { + spin_lock(&engine->i915->shared_page_lock); + elsp_data = engine->i915->shared_page->elsp_data; + *elsp_data = 0; + *(elsp_data + 1) = 0; + *(elsp_data + 2) = upper_32_bits(ce->lrc_desc); + writel(lower_32_bits(ce->lrc_desc), elsp); + spin_unlock(&engine->i915->shared_page_lock); + return; + } + /* * Switch to our empty preempt context so * the state of the GPU is known (idle).