| Message ID | 1540228395-27377-1-git-send-email-tomasz.lis@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] drm/i915/icl: Define MOCS table for Icelake | expand |
On 22/10/18 10:13, Tomasz Lis wrote: > The table has been unified across OSes to minimize virtualization overhead. > > The MOCS table is now published as part of bspec, and versioned. Entries > are supposed to never be modified, but new ones can be added. Adding > entries increases table version. The patch includes version 1 entries. > > Meaning of each entry is now explained in bspec, and user mode clients > are expected to know what each entry means. The 3 entries used for previous > platforms are still compatible with their legacy definitions, but that is > not guaranteed to be true for future platforms. > > BSpec: 34007 > BSpec: 560 > Signed-off-by: Tomasz Lis <tomasz.lis@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Zhenyu Wang <zhenyuw@linux.intel.com> > Cc: Zhi A Wang <zhi.a.wang@intel.com> > Cc: Anuj Phogat <anuj.phogat@intel.com> > --- > drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++- > 1 file changed, 244 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index 77e9871..dc34e83 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -44,6 +44,8 @@ struct drm_i915_mocs_table { > #define LE_SCC(value) ((value) << 8) > #define LE_PFM(value) ((value) << 11) > #define LE_SCF(value) ((value) << 14) > +#define LE_CoS(value) ((value) << 15) > +#define LE_SSE(value) ((value) << 17) > > /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ > #define L3_ESC(value) ((value) << 0) > @@ -96,6 +98,243 @@ struct drm_i915_mocs_table { > * may only be updated incrementally by adding entries at the > * end. > */ This comment needs to be updated as some of the expectations are not true anymore, e.g. we're now defining entries 62 and 63 in SW, usage of mocs 0 is changing. Also could be useful to add some of the info you have in the commit message here, like the fact that the table is versioned in the specs for gen11+, so it is close to the table. From a POV of following the specs, with the updated comments this is: Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> But please get acks from the relevant interested parties to make sure there are no concerns with the new approach. Also having someone else double-check the table as well would be nice since I might have missed something and it's going to be hard to catch issues in testing if the only impact is a very small performance delta. Thanks, Daniele > +static const struct drm_i915_mocs_entry icelake_mocs_table[] = { > + [0] = { > + /* Base - Uncached (Deprecated) */ > + .control_value = LE_CACHEABILITY(LE_UC) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [1] = { > + /* Base - L3 + LeCC:PAT (Deprecated) */ > + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [2] = { > + /* Base - L3 + LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [3] = { > + /* Base - Uncached */ > + .control_value = LE_CACHEABILITY(LE_UC) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [4] = { > + /* Base - L3 */ > + .control_value = LE_CACHEABILITY(LE_UC) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [5] = { > + /* Base - LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [6] = { > + /* Age 0 - LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [7] = { > + /* Age 0 - L3 + LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [8] = { > + /* Age: Don't Chg. - LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [9] = { > + /* Age: Don't Chg. - L3 + LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [10] = { > + /* No AOM - LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [11] = { > + /* No AOM - L3 + LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [12] = { > + /* No AOM; Age 0 - LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [13] = { > + /* No AOM; Age 0 - L3 + LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [14] = { > + /* No AOM; Age:DC - LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [15] = { > + /* No AOM; Age:DC - L3 + LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [16] = { > + /* Reserved - For future use */ > + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | > + LE_TGT_CACHE(LE_TC_PAGETABLE) | > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT), > + }, > + [17] = { > + /* Reserved - For future use */ > + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | > + LE_TGT_CACHE(LE_TC_PAGETABLE) | > + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT), > + }, > + [18] = { > + /* Self-Snoop - L3 + LLC */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [19] = { > + /* Skip Caching - L3 + LLC(12.5%) */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [20] = { > + /* Skip Caching - L3 + LLC(25%) */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [21] = { > + /* Skip Caching - L3 + LLC(50%) */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [22] = { > + /* Skip Caching - L3 + LLC(75%) */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [23] = { > + /* Skip Caching - L3 + LLC(87.5%) */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), > + }, > + [62] = { > + /* HW Reserved - SW program but never use */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > + [63] = { > + /* HW Reserved - SW program but never use */ > + .control_value = LE_CACHEABILITY(LE_WB) | > + LE_TGT_CACHE(LE_TC_LLC) | > + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | > + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), > + > + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), > + }, > +}; > + > static const struct drm_i915_mocs_entry skylake_mocs_table[] = { > [I915_MOCS_UNCACHED] = { > /* 0x00000009 */ > @@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, > { > bool result = false; > > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || > - IS_ICELAKE(dev_priv)) { > + if (IS_ICELAKE(dev_priv)) { > + table->size = ARRAY_SIZE(icelake_mocs_table); > + table->table = icelake_mocs_table; > + result = true; > + } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { > table->size = ARRAY_SIZE(skylake_mocs_table); > table->table = skylake_mocs_table; > result = true; >
On 2018-10-22 19:40, Daniele Ceraolo Spurio wrote: > > > On 22/10/18 10:13, Tomasz Lis wrote: >> The table has been unified across OSes to minimize virtualization >> overhead. >> >> The MOCS table is now published as part of bspec, and versioned. Entries >> are supposed to never be modified, but new ones can be added. Adding >> entries increases table version. The patch includes version 1 entries. >> >> Meaning of each entry is now explained in bspec, and user mode clients >> are expected to know what each entry means. The 3 entries used for >> previous >> platforms are still compatible with their legacy definitions, but >> that is >> not guaranteed to be true for future platforms. >> >> BSpec: 34007 >> BSpec: 560 >> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com> >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: Mika Kuoppala <mika.kuoppala@intel.com> >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> >> Cc: Zhi A Wang <zhi.a.wang@intel.com> >> Cc: Anuj Phogat <anuj.phogat@intel.com> >> --- >> drivers/gpu/drm/i915/intel_mocs.c | 246 >> +++++++++++++++++++++++++++++++++++++- >> 1 file changed, 244 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_mocs.c >> b/drivers/gpu/drm/i915/intel_mocs.c >> index 77e9871..dc34e83 100644 >> --- a/drivers/gpu/drm/i915/intel_mocs.c >> +++ b/drivers/gpu/drm/i915/intel_mocs.c >> @@ -44,6 +44,8 @@ struct drm_i915_mocs_table { >> #define LE_SCC(value) ((value) << 8) >> #define LE_PFM(value) ((value) << 11) >> #define LE_SCF(value) ((value) << 14) >> +#define LE_CoS(value) ((value) << 15) >> +#define LE_SSE(value) ((value) << 17) >> /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries >> per word */ >> #define L3_ESC(value) ((value) << 0) >> @@ -96,6 +98,243 @@ struct drm_i915_mocs_table { >> * may only be updated incrementally by adding entries at the >> * end. >> */ > > This comment needs to be updated as some of the expectations are not > true anymore, e.g. we're now defining entries 62 and 63 in SW, usage > of mocs 0 is changing. Also could be useful to add some of the info > you have in the commit message here, like the fact that the table is > versioned in the specs for gen11+, so it is close to the table. > > From a POV of following the specs, with the updated comments this is: > > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > > But please get acks from the relevant interested parties to make sure > there are no concerns with the new approach. I believe all parties are informed; will add some more cc's to v3. > Also having someone else double-check the table as well would be nice > since I might have missed something and it's going to be hard to catch > issues in testing if the only impact is a very small performance delta. > > Thanks, > Daniele The IGT test for MOCS settings compares explicitly content of the registers with expected values hard-coded into that test; since someone else than me will be updating that test for correct Icelake values, we can count that as second verification. -Tomasz > >> +static const struct drm_i915_mocs_entry icelake_mocs_table[] = { >> + [0] = { >> + /* Base - Uncached (Deprecated) */ >> + .control_value = LE_CACHEABILITY(LE_UC) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [1] = { >> + /* Base - L3 + LeCC:PAT (Deprecated) */ >> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [2] = { >> + /* Base - L3 + LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [3] = { >> + /* Base - Uncached */ >> + .control_value = LE_CACHEABILITY(LE_UC) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [4] = { >> + /* Base - L3 */ >> + .control_value = LE_CACHEABILITY(LE_UC) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [5] = { >> + /* Base - LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [6] = { >> + /* Age 0 - LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [7] = { >> + /* Age 0 - L3 + LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [8] = { >> + /* Age: Don't Chg. - LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [9] = { >> + /* Age: Don't Chg. - L3 + LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [10] = { >> + /* No AOM - LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [11] = { >> + /* No AOM - L3 + LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [12] = { >> + /* No AOM; Age 0 - LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [13] = { >> + /* No AOM; Age 0 - L3 + LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [14] = { >> + /* No AOM; Age:DC - LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [15] = { >> + /* No AOM; Age:DC - L3 + LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [16] = { >> + /* Reserved - For future use */ >> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | >> + LE_TGT_CACHE(LE_TC_PAGETABLE) | >> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | >> L3_CACHEABILITY(L3_DIRECT), >> + }, >> + [17] = { >> + /* Reserved - For future use */ >> + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | >> + LE_TGT_CACHE(LE_TC_PAGETABLE) | >> + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | >> L3_CACHEABILITY(L3_DIRECT), >> + }, >> + [18] = { >> + /* Self-Snoop - L3 + LLC */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [19] = { >> + /* Skip Caching - L3 + LLC(12.5%) */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [20] = { >> + /* Skip Caching - L3 + LLC(25%) */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [21] = { >> + /* Skip Caching - L3 + LLC(50%) */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [22] = { >> + /* Skip Caching - L3 + LLC(75%) */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [23] = { >> + /* Skip Caching - L3 + LLC(87.5%) */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), >> + }, >> + [62] = { >> + /* HW Reserved - SW program but never use */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> + [63] = { >> + /* HW Reserved - SW program but never use */ >> + .control_value = LE_CACHEABILITY(LE_WB) | >> + LE_TGT_CACHE(LE_TC_LLC) | >> + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | >> + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), >> + >> + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), >> + }, >> +}; >> + >> static const struct drm_i915_mocs_entry skylake_mocs_table[] = { >> [I915_MOCS_UNCACHED] = { >> /* 0x00000009 */ >> @@ -178,8 +417,11 @@ static bool get_mocs_settings(struct >> drm_i915_private *dev_priv, >> { >> bool result = false; >> - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || >> - IS_ICELAKE(dev_priv)) { >> + if (IS_ICELAKE(dev_priv)) { >> + table->size = ARRAY_SIZE(icelake_mocs_table); >> + table->table = icelake_mocs_table; >> + result = true; >> + } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { >> table->size = ARRAY_SIZE(skylake_mocs_table); >> table->table = skylake_mocs_table; >> result = true; >>
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 77e9871..dc34e83 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -44,6 +44,8 @@ struct drm_i915_mocs_table { #define LE_SCC(value) ((value) << 8) #define LE_PFM(value) ((value) << 11) #define LE_SCF(value) ((value) << 14) +#define LE_CoS(value) ((value) << 15) +#define LE_SSE(value) ((value) << 17) /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ #define L3_ESC(value) ((value) << 0) @@ -96,6 +98,243 @@ struct drm_i915_mocs_table { * may only be updated incrementally by adding entries at the * end. */ +static const struct drm_i915_mocs_entry icelake_mocs_table[] = { + [0] = { + /* Base - Uncached (Deprecated) */ + .control_value = LE_CACHEABILITY(LE_UC) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [1] = { + /* Base - L3 + LeCC:PAT (Deprecated) */ + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [2] = { + /* Base - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [3] = { + /* Base - Uncached */ + .control_value = LE_CACHEABILITY(LE_UC) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [4] = { + /* Base - L3 */ + .control_value = LE_CACHEABILITY(LE_UC) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [5] = { + /* Base - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [6] = { + /* Age 0 - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [7] = { + /* Age 0 - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [8] = { + /* Age: Don't Chg. - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [9] = { + /* Age: Don't Chg. - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [10] = { + /* No AOM - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [11] = { + /* No AOM - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [12] = { + /* No AOM; Age 0 - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [13] = { + /* No AOM; Age 0 - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [14] = { + /* No AOM; Age:DC - LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [15] = { + /* No AOM; Age:DC - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [16] = { + /* Reserved - For future use */ + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | + LE_TGT_CACHE(LE_TC_PAGETABLE) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT), + }, + [17] = { + /* Reserved - For future use */ + .control_value = LE_CACHEABILITY(LE_PAGETABLE) | + LE_TGT_CACHE(LE_TC_PAGETABLE) | + LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT), + }, + [18] = { + /* Self-Snoop - L3 + LLC */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [19] = { + /* Skip Caching - L3 + LLC(12.5%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [20] = { + /* Skip Caching - L3 + LLC(25%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [21] = { + /* Skip Caching - L3 + LLC(50%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [22] = { + /* Skip Caching - L3 + LLC(75%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [23] = { + /* Skip Caching - L3 + LLC(87.5%) */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), + }, + [62] = { + /* HW Reserved - SW program but never use */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, + [63] = { + /* HW Reserved - SW program but never use */ + .control_value = LE_CACHEABILITY(LE_WB) | + LE_TGT_CACHE(LE_TC_LLC) | + LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | + LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), + + .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), + }, +}; + static const struct drm_i915_mocs_entry skylake_mocs_table[] = { [I915_MOCS_UNCACHED] = { /* 0x00000009 */ @@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, { bool result = false; - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || - IS_ICELAKE(dev_priv)) { + if (IS_ICELAKE(dev_priv)) { + table->size = ARRAY_SIZE(icelake_mocs_table); + table->table = icelake_mocs_table; + result = true; + } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { table->size = ARRAY_SIZE(skylake_mocs_table); table->table = skylake_mocs_table; result = true;
The table has been unified across OSes to minimize virtualization overhead. The MOCS table is now published as part of bspec, and versioned. Entries are supposed to never be modified, but new ones can be added. Adding entries increases table version. The patch includes version 1 entries. Meaning of each entry is now explained in bspec, and user mode clients are expected to know what each entry means. The 3 entries used for previous platforms are still compatible with their legacy definitions, but that is not guaranteed to be true for future platforms. BSpec: 34007 BSpec: 560 Signed-off-by: Tomasz Lis <tomasz.lis@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhi A Wang <zhi.a.wang@intel.com> Cc: Anuj Phogat <anuj.phogat@intel.com> --- drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++- 1 file changed, 244 insertions(+), 2 deletions(-)