From patchwork Mon Oct 22 17:13:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lis, Tomasz" X-Patchwork-Id: 10652261 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D9B2814BB for ; Mon, 22 Oct 2018 17:13:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EEDF82074F for ; Mon, 22 Oct 2018 17:13:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E316B2521E; Mon, 22 Oct 2018 17:13:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 851D32074F for ; Mon, 22 Oct 2018 17:13:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DC5B89CE0; Mon, 22 Oct 2018 17:13:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4F1D0893EF for ; Mon, 22 Oct 2018 17:13:20 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Oct 2018 10:13:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,412,1534834800"; d="scan'208";a="99691385" Received: from szara.igk.intel.com ([172.28.178.192]) by fmsmga004.fm.intel.com with ESMTP; 22 Oct 2018 10:13:18 -0700 From: Tomasz Lis To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Oct 2018 19:13:15 +0200 Message-Id: <1540228395-27377-2-git-send-email-tomasz.lis@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1540228395-27377-1-git-send-email-tomasz.lis@intel.com> References: <1539962368-5451-1-git-send-email-tomasz.lis@intel.com> <1540228395-27377-1-git-send-email-tomasz.lis@intel.com> Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anuj Phogat , Mika Kuoppala MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For Icelake and above, MOCS table for each platform is published within bspec. The table is versioned, and new entries are assigned a version number. Existing entries do not change and their version is constant. This introduces a parameter which allows getting max version number of the MOCS entries currently supported, ie. value of 2 would mean only version 1 and version 2 entries are initialized and can be used by the user mode clients. BSpec: 34007 Signed-off-by: Tomasz Lis Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Mika Kuoppala Cc: Daniele Ceraolo Spurio Cc: Zhenyu Wang Cc: Zhi A Wang Cc: Anuj Phogat --- drivers/gpu/drm/i915/i915_drv.c | 6 ++++++ drivers/gpu/drm/i915/intel_mocs.c | 12 ++++++++++++ drivers/gpu/drm/i915/intel_mocs.h | 1 + include/uapi/drm/i915_drm.h | 11 +++++++++++ 4 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index baac35f..92fa8fd 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -53,6 +53,7 @@ #include "i915_vgpu.h" #include "intel_drv.h" #include "intel_uc.h" +#include "intel_mocs.h" static struct drm_driver driver; @@ -444,6 +445,11 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data, case I915_PARAM_MMAP_GTT_COHERENT: value = INTEL_INFO(dev_priv)->has_coherent_ggtt; break; + case I915_PARAM_MOCS_TABLE_VERSION: + value = intel_mocs_table_version(dev_priv); + if (!value) + return -ENODEV; + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index dc34e83..fc1e98b 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -469,6 +469,18 @@ static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index) } /** + * intel_mocs_table_version() - get version of mocs table implementation + * @i915: i915 device struct. + */ +int intel_mocs_table_version(struct drm_i915_private *i915) +{ + if (IS_ICELAKE(i915)) + return 1; + else + return 0; +} + +/** * intel_mocs_init_engine() - emit the mocs control table * @engine: The engine for whom to emit the registers. * diff --git a/drivers/gpu/drm/i915/intel_mocs.h b/drivers/gpu/drm/i915/intel_mocs.h index d89080d..dc1d64a 100644 --- a/drivers/gpu/drm/i915/intel_mocs.h +++ b/drivers/gpu/drm/i915/intel_mocs.h @@ -55,5 +55,6 @@ int intel_rcs_context_init_mocs(struct i915_request *rq); void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv); void intel_mocs_init_engine(struct intel_engine_cs *engine); +int intel_mocs_table_version(struct drm_i915_private *i915); #endif diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 298b2e1..16aafc4 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -559,6 +559,17 @@ typedef struct drm_i915_irq_wait { */ #define I915_PARAM_MMAP_GTT_COHERENT 52 +/* + * Query MOCS table version used during hardware initialization. + * + * The MOCS table for each platform is published as part of bspec. Entries in + * the table are supposed to never be modified, but new enties are added, making + * more indexes in the table valid. This parameter informs which version + * of the table was used to initialize the currently used graphics hardware, + * and therefore which MOCS indexes are useable. + */ +#define I915_PARAM_MOCS_TABLE_VERSION 53 + typedef struct drm_i915_getparam { __s32 param; /*