From patchwork Tue Oct 23 20:40:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10653625 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9CB0013A9 for ; Tue, 23 Oct 2018 20:21:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8C4582A434 for ; Tue, 23 Oct 2018 20:21:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 80EBE2A42B; Tue, 23 Oct 2018 20:21:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1EF912A42C for ; Tue, 23 Oct 2018 20:21:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C8226E0E5; Tue, 23 Oct 2018 20:21:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id CAB6B6E0BF for ; Tue, 23 Oct 2018 20:20:59 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Oct 2018 13:20:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,417,1534834800"; d="scan'208";a="83863032" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by orsmga008.jf.intel.com with ESMTP; 23 Oct 2018 13:20:57 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Wed, 24 Oct 2018 02:10:54 +0530 Message-Id: <1540327255-25639-3-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1540327255-25639-1-git-send-email-uma.shankar@intel.com> References: <1540327255-25639-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and gamma support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add support for icl pipe degamma and gamma. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 3 ++ drivers/gpu/drm/i915/intel_color.c | 75 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8bd61f9..dd0514e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6965,6 +6965,9 @@ enum { #define GAMMA_MODE_MODE_12BIT (2 << 0) #define GAMMA_MODE_MODE_SPLIT (3 << 0) +#define PRE_CSC_GAMMA_ENABLE (1 << 31) +#define POST_CSC_GAMMA_ENABLE (1 << 31) + /* DMC/CSR */ #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 5127da2..7860244 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -424,6 +424,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset) struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); enum pipe pipe = to_intel_crtc(state->crtc)->pipe; uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + uint32_t tmp; WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK); @@ -464,6 +465,11 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset) I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1); I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1); } + + if (IS_ICELAKE(dev_priv)) { + tmp = I915_READ(GAMMA_MODE(pipe)); + I915_WRITE(GAMMA_MODE(pipe), tmp | POST_CSC_GAMMA_ENABLE); + } } /* Loads the palette/gamma unit for the CRTC on Broadwell+. */ @@ -523,6 +529,50 @@ static void glk_load_degamma_lut(struct drm_crtc_state *state) I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); } +static void icl_load_degamma_lut(struct drm_crtc_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); + enum pipe pipe = to_intel_crtc(state->crtc)->pipe; + const uint32_t lut_size = 33; + uint32_t tmp, i; + + /* + * When setting the auto-increment bit, the hardware seems to + * ignore the index bits, so we need to reset it to index 0 + * separately. + */ + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0); + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT); + + if (state->degamma_lut) { + struct drm_color_lut *lut = + (struct drm_color_lut *) state->degamma_lut->data; + for (i = 0; i < lut_size; i++) { + /* + * Currently Clamp input to 1.0. + * ToDo: Extend to max 7.0. + */ + uint32_t word = + drm_color_lut_extract(lut[i].red, 16); + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), word); + } + } else { + /* load a linear table. */ + for (i = 0; i < lut_size; i++) { + uint32_t v = (i * (1 << 16)) / (lut_size - 1); + + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v); + } + } + + tmp = I915_READ(GAMMA_MODE(pipe)); + I915_WRITE(GAMMA_MODE(pipe), tmp | PRE_CSC_GAMMA_ENABLE); + + /* Clamp values > 1.0. */ + while (i++ < 35) + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); +} + static void glk_load_luts(struct drm_crtc_state *state) { struct drm_crtc *crtc = state->crtc; @@ -606,6 +656,29 @@ static void cherryview_load_luts(struct drm_crtc_state *state) i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state)); } +static void icl_load_luts(struct drm_crtc_state *state) +{ + struct drm_crtc *crtc = state->crtc; + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc_state *intel_state = to_intel_crtc_state(state); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + + icl_load_degamma_lut(state); + + if (crtc_state_is_legacy_gamma(state)) { + haswell_load_luts(state); + return; + } + + bdw_load_gamma_lut(state, 0); + intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT; + + I915_WRITE(GAMMA_MODE(pipe), I915_READ(GAMMA_MODE(pipe)) | + intel_state->gamma_mode); + POSTING_READ(GAMMA_MODE(pipe)); +} + void intel_color_load_luts(struct drm_crtc_state *crtc_state) { struct drm_device *dev = crtc_state->crtc->dev; @@ -662,6 +735,8 @@ void intel_color_init(struct drm_crtc *crtc) } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { dev_priv->display.load_csc_matrix = ilk_load_csc_matrix; dev_priv->display.load_luts = glk_load_luts; + } else if (IS_ICELAKE(dev_priv)) { + dev_priv->display.load_luts = icl_load_luts; } else { dev_priv->display.load_luts = i9xx_load_luts; }