From patchwork Tue Nov 6 04:13:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Navik X-Patchwork-Id: 10669597 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C10014BD for ; Tue, 6 Nov 2018 04:13:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 27AFE206AF for ; Tue, 6 Nov 2018 04:13:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 17A422A071; Tue, 6 Nov 2018 04:13:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8694E2A06E for ; Tue, 6 Nov 2018 04:13:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0622E6E28D; Tue, 6 Nov 2018 04:13:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1DE716E28D for ; Tue, 6 Nov 2018 04:13:22 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Nov 2018 20:13:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,470,1534834800"; d="scan'208";a="278644844" Received: from apnavik-desk.iind.intel.com ([10.66.247.186]) by fmsmga006.fm.intel.com with ESMTP; 05 Nov 2018 20:13:21 -0800 From: Ankit Navik To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Nov 2018 09:43:20 +0530 Message-Id: <1541477601-10883-4-git-send-email-ankit.p.navik@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1541477601-10883-1-git-send-email-ankit.p.navik@intel.com> References: <1541477601-10883-1-git-send-email-ankit.p.navik@intel.com> Subject: [Intel-gfx] [PATCH v2 3/4] drm/i915: set optimum eu/slice/sub-slice configuration based on load type X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Praveen Diwakar This patch will select optimum eu/slice/sub-slice configuration based on type of load (low, medium, high) as input. Based on our readings and experiments we have predefined set of optimum configuration for each platform(CHT, KBL). i915_gem_context_set_load_type will select optimum configuration from pre-defined optimum configuration table(opt_config). It also introduce flag update_render_config which can set by any governor. Signed-off-by: Praveen Diwakar Signed-off-by: Yogesh Marathe Signed-off-by: Aravindan Muthukumar Signed-off-by: Kedar J Karanje Signed-off-by: Ankit Navik Suggested-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem_context.c | 21 +++++++++++++++ drivers/gpu/drm/i915/i915_gem_context.h | 30 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_device_info.c | 44 ++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_lrc.c | 4 ++- 5 files changed, 98 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 137ec33..f1b16d0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1686,6 +1686,8 @@ struct drm_i915_private { struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ int num_fence_regs; /* 8 on pre-965, 16 otherwise */ + struct optimum_config opt_config[LOAD_TYPE_MAX]; + unsigned int fsb_freq, mem_freq, is_ddr3; unsigned int skl_preferred_vco_freq; unsigned int max_cdclk_freq; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index d040858..28ff868 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -388,14 +388,35 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, trace_i915_context_create(ctx); atomic_set(&ctx->req_cnt, 0); + ctx->update_render_config = 0; ctx->slice_cnt = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask); ctx->subslice_cnt = hweight8( INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); ctx->eu_cnt = INTEL_INFO(dev_priv)->sseu.eu_per_subslice; + ctx->load_type = 0; + ctx->pending_load_type = 0; return ctx; } + +void i915_gem_context_set_load_type(struct i915_gem_context *ctx, + enum gem_load_type type) +{ + struct drm_i915_private *dev_priv = ctx->i915; + + /* Call opt_config to get correct configuration for eu,slice,subslice */ + ctx->slice_cnt = dev_priv->opt_config[type].slice; + ctx->subslice_cnt = dev_priv->opt_config[type].subslice; + ctx->eu_cnt = dev_priv->opt_config[type].eu; + + /* Enabling this to update the rpcs */ + if (ctx->pending_load_type != type) + ctx->update_render_config = 1; + + ctx->pending_load_type = type; +} + /** * i915_gem_context_create_gvt - create a GVT GEM context * @dev: drm device * diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 2b3bf09..9345aa3 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -53,6 +53,19 @@ struct intel_context_ops { void (*destroy)(struct intel_context *ce); }; +enum gem_load_type { + LOAD_TYPE_LOW, + LOAD_TYPE_MEDIUM, + LOAD_TYPE_HIGH, + LOAD_TYPE_MAX +}; + +struct optimum_config { + u8 slice; + u8 subslice; + u8 eu; +}; + /** * struct i915_gem_context - client state * @@ -209,6 +222,21 @@ struct i915_gem_context { /** eu_cnt: used to set the # of eu to be enabled. */ u8 eu_cnt; + + /** update_render_config: to track the updates to the render + * configuration (S/SS/EU Configuration on the GPU) + */ + bool update_render_config; + + /** load_type: The designated load_type (high/medium/low) for a given + * number of pending commands in the command queue. + */ + enum gem_load_type load_type; + + /** pending_load_type: The earlier load type that the GPU was configured + * for (high/medium/low). + */ + enum gem_load_type pending_load_type; }; static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx) @@ -337,6 +365,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +void i915_gem_context_set_load_type(struct i915_gem_context *ctx, + enum gem_load_type type); struct i915_gem_context * i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio); diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 0ef0c64..4c6224a 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -741,6 +741,27 @@ void intel_device_info_runtime_init(struct intel_device_info *info) container_of(info, struct drm_i915_private, info); enum pipe pipe; + /* static table of slice/subslice/EU for Cherrytrial */ + struct optimum_config chv_config[LOAD_TYPE_MAX] = { + {1, 1, 4}, /* Low */ + {1, 1, 6}, /* Medium */ + {1, 2, 6} /* High */ + }; + + /* static table of slice/subslice/EU for KBL GT2 */ + struct optimum_config kbl_gt2_config[LOAD_TYPE_MAX] = { + {1, 3, 2}, /* Low */ + {1, 3, 4}, /* Medium */ + {1, 3, 8} /* High */ + }; + + /* static table of slice/subslice/EU for KBL GT3 */ + struct optimum_config kbl_gt3_config[LOAD_TYPE_MAX] = { + {2, 3, 4}, /* Low */ + {2, 3, 6}, /* Medium */ + {2, 3, 8} /* High */ + }; + if (INTEL_GEN(dev_priv) >= 10) { for_each_pipe(dev_priv, pipe) info->num_scalers[pipe] = 2; @@ -840,12 +861,31 @@ void intel_device_info_runtime_init(struct intel_device_info *info) /* Initialize slice/subslice/EU info */ if (IS_HASWELL(dev_priv)) haswell_sseu_info_init(dev_priv); - else if (IS_CHERRYVIEW(dev_priv)) + else if (IS_CHERRYVIEW(dev_priv)) { cherryview_sseu_info_init(dev_priv); + memcpy(dev_priv->opt_config, chv_config, sizeof(chv_config)); + } else if (IS_BROADWELL(dev_priv)) broadwell_sseu_info_init(dev_priv); - else if (INTEL_GEN(dev_priv) == 9) + else if (INTEL_GEN(dev_priv) == 9) { gen9_sseu_info_init(dev_priv); + + if (IS_KABYLAKE(dev_priv)) { + switch (info->gt) { + default: + MISSING_CASE(info->gt); + /* fall through */ + case 2: + memcpy(dev_priv->opt_config, kbl_gt2_config, + sizeof(kbl_gt2_config)); + break; + case 3: + memcpy(dev_priv->opt_config, kbl_gt3_config, + sizeof(kbl_gt3_config)); + break; + } + } + } else if (INTEL_GEN(dev_priv) == 10) gen10_sseu_info_init(dev_priv); else if (INTEL_GEN(dev_priv) >= 11) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index a8ab71a..4d000eb 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -427,11 +427,13 @@ static u64 execlists_update_context(struct i915_request *rq) reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); /* FIXME: To avoid stale rpcs config, move it to context_pin */ - if (ctx->pid && ctx->name && (rq->engine->id == RCS)) { + if (ctx->pid && ctx->name && (rq->engine->id == RCS) && + ctx->update_render_config) { rpcs_config = make_rpcs(ctx->i915); reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, rpcs_config); + ctx->update_render_config = 0; } /* True 32b PPGTT with dynamic page allocation: update PDP