| Message ID | 1543327379-22629-2-git-send-email-ramalingam.c@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | HDCP1.4 fixes | expand |
On Tue, Nov 27, 2018 at 07:32:56PM +0530, Ramalingam C wrote: > HDCP1.4 key load process varies between Intel platform to platform. > > For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using > the GT Driver Mailbox interface. Instead of listing all the platforms > for this method, adopted this method for all Gen9 platforms with > exceptions. In this way we need not extent check for new GEN9 platforms > like CFL. > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > --- > drivers/gpu/drm/i915/intel_hdcp.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c > index 1bf487f94254..beacfbb6e5e1 100644 > --- a/drivers/gpu/drm/i915/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/intel_hdcp.c > @@ -157,10 +157,12 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) > /* > * Initiate loading the HDCP key from fuses. > * > - * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL > - * differ in the key load trigger process from other platforms. > + * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9 > + * platforms except BXT and GLK, differ in the key load trigger process > + * from other platforms. > */ > - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { > + if (IS_GEN9(dev_priv) && > + (!IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv))) { IS_GEN9_BC() > mutex_lock(&dev_priv->pcu_lock); > ret = sandybridge_pcode_write(dev_priv, > SKL_PCODE_LOAD_HDCP_KEYS, 1); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 11/27/2018 8:45 PM, Ville Syrjälä wrote: > On Tue, Nov 27, 2018 at 07:32:56PM +0530, Ramalingam C wrote: >> HDCP1.4 key load process varies between Intel platform to platform. >> >> For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using >> the GT Driver Mailbox interface. Instead of listing all the platforms >> for this method, adopted this method for all Gen9 platforms with >> exceptions. In this way we need not extent check for new GEN9 platforms >> like CFL. >> >> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> >> --- >> drivers/gpu/drm/i915/intel_hdcp.c | 8 +++++--- >> 1 file changed, 5 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c >> index 1bf487f94254..beacfbb6e5e1 100644 >> --- a/drivers/gpu/drm/i915/intel_hdcp.c >> +++ b/drivers/gpu/drm/i915/intel_hdcp.c >> @@ -157,10 +157,12 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) >> /* >> * Initiate loading the HDCP key from fuses. >> * >> - * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL >> - * differ in the key load trigger process from other platforms. >> + * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9 >> + * platforms except BXT and GLK, differ in the key load trigger process >> + * from other platforms. >> */ >> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { >> + if (IS_GEN9(dev_priv) && >> + (!IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv))) { > IS_GEN9_BC() Bspec doesn't state anything about BC/LP. They have mentioned GEN9+ with BXT, CNL, ICL excluded. So I am inferring that this method is only for Gen9 excluding BXT and GLK (verified). Remaining platforms are SKL, KBL, and CFL. IS_GEN9_BC() will filter them easily. unless we find otherwise, we can use this. Thanks Ville. --Ram > >> mutex_lock(&dev_priv->pcu_lock); >> ret = sandybridge_pcode_write(dev_priv, >> SKL_PCODE_LOAD_HDCP_KEYS, 1); >> -- >> 2.7.4 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx <html> <head> <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"> </head> <body text="#000000" bgcolor="#FFFFFF"> <p><br> </p> <div class="moz-cite-prefix">On 11/27/2018 8:45 PM, Ville Syrjälä wrote:<br> </div> <blockquote type="cite" cite="mid:20181127151545.GZ9144@intel.com"> <pre class="moz-quote-pre" wrap="">On Tue, Nov 27, 2018 at 07:32:56PM +0530, Ramalingam C wrote: </pre> <blockquote type="cite"> <pre class="moz-quote-pre" wrap="">HDCP1.4 key load process varies between Intel platform to platform. For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using the GT Driver Mailbox interface. Instead of listing all the platforms for this method, adopted this method for all Gen9 platforms with exceptions. In this way we need not extent check for new GEN9 platforms like CFL. Signed-off-by: Ramalingam C <a class="moz-txt-link-rfc2396E" href="mailto:ramalingam.c@intel.com"><ramalingam.c@intel.com></a> --- drivers/gpu/drm/i915/intel_hdcp.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c index 1bf487f94254..beacfbb6e5e1 100644 --- a/drivers/gpu/drm/i915/intel_hdcp.c +++ b/drivers/gpu/drm/i915/intel_hdcp.c @@ -157,10 +157,12 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) /* * Initiate loading the HDCP key from fuses. * - * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL - * differ in the key load trigger process from other platforms. + * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9 + * platforms except BXT and GLK, differ in the key load trigger process + * from other platforms. */ - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { + if (IS_GEN9(dev_priv) && + (!IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv))) { </pre> </blockquote> <pre class="moz-quote-pre" wrap=""> IS_GEN9_BC()</pre> </blockquote> <pre>Bspec doesn't state anything about BC/LP. They have mentioned GEN9+ with BXT, CNL, ICL excluded. So I am inferring that this method is only for Gen9 excluding BXT and GLK (verified). Remaining platforms are SKL, KBL, and CFL. IS_GEN9_BC() will filter them easily. unless we find otherwise, we can use this. Thanks Ville. --Ram </pre> <blockquote type="cite" cite="mid:20181127151545.GZ9144@intel.com"> <pre class="moz-quote-pre" wrap=""> </pre> <blockquote type="cite"> <pre class="moz-quote-pre" wrap=""> mutex_lock(&dev_priv->pcu_lock); ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
On Tue, Nov 27, 2018 at 07:32:56PM +0530, Ramalingam C wrote: > HDCP1.4 key load process varies between Intel platform to platform. > > For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using > the GT Driver Mailbox interface. Instead of listing all the platforms > for this method, adopted this method for all Gen9 platforms with > exceptions. In this way we need not extent check for new GEN9 platforms > like CFL. > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Sean Paul <sean@poorly.run> > --- > drivers/gpu/drm/i915/intel_hdcp.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c > index 1bf487f94254..beacfbb6e5e1 100644 > --- a/drivers/gpu/drm/i915/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/intel_hdcp.c > @@ -157,10 +157,12 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) > /* > * Initiate loading the HDCP key from fuses. > * > - * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL > - * differ in the key load trigger process from other platforms. > + * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9 > + * platforms except BXT and GLK, differ in the key load trigger process > + * from other platforms. > */ > - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { > + if (IS_GEN9(dev_priv) && > + (!IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv))) { > mutex_lock(&dev_priv->pcu_lock); > ret = sandybridge_pcode_write(dev_priv, > SKL_PCODE_LOAD_HDCP_KEYS, 1); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c index 1bf487f94254..beacfbb6e5e1 100644 --- a/drivers/gpu/drm/i915/intel_hdcp.c +++ b/drivers/gpu/drm/i915/intel_hdcp.c @@ -157,10 +157,12 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) /* * Initiate loading the HDCP key from fuses. * - * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL - * differ in the key load trigger process from other platforms. + * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9 + * platforms except BXT and GLK, differ in the key load trigger process + * from other platforms. */ - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { + if (IS_GEN9(dev_priv) && + (!IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv))) { mutex_lock(&dev_priv->pcu_lock); ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
HDCP1.4 key load process varies between Intel platform to platform. For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using the GT Driver Mailbox interface. Instead of listing all the platforms for this method, adopted this method for all Gen9 platforms with exceptions. In this way we need not extent check for new GEN9 platforms like CFL. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/intel_hdcp.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)