From patchwork Tue Dec 11 10:14:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Navik X-Patchwork-Id: 10723393 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8B321869 for ; Tue, 11 Dec 2018 10:13:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA2912A473 for ; Tue, 11 Dec 2018 10:13:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BED0D2A47C; Tue, 11 Dec 2018 10:13:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 61D4B2A473 for ; Tue, 11 Dec 2018 10:13:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CA2566E046; Tue, 11 Dec 2018 10:13:15 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 70E1C6E046 for ; Tue, 11 Dec 2018 10:13:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Dec 2018 02:13:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,342,1539673200"; d="scan'208";a="108638938" Received: from apnavik-desk.iind.intel.com ([10.66.247.186]) by fmsmga008.fm.intel.com with ESMTP; 11 Dec 2018 02:13:12 -0800 From: Ankit Navik To: intel-gfx@lists.freedesktop.org Date: Tue, 11 Dec 2018 15:44:19 +0530 Message-Id: <1544523261-26905-3-git-send-email-ankit.p.navik@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544523261-26905-1-git-send-email-ankit.p.navik@intel.com> References: <1544523261-26905-1-git-send-email-ankit.p.navik@intel.com> Subject: [Intel-gfx] [PATCH v3 2/4] drm/i915: Update render power clock state configuration for given context X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ankit.p.navik@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Praveen Diwakar This patch will update power clock state register at runtime base on the flag which can set by any governor which computes load and want to update rpcs register. subsequent patches will have a timer based governor which computes pending load/request. V2: * Reuse make_rpcs to get rpcs config. (Tvrtko Ursulin) V3: * Rebase. Cc: Aravindan Muthukumar Cc: Kedar J Karanje Cc: Yogesh Marathe Reviewed-by: Tvrtko Ursulin Signed-off-by: Praveen Diwakar Signed-off-by: Ankit Navik --- drivers/gpu/drm/i915/i915_gem_context.c | 4 ++++ drivers/gpu/drm/i915/i915_gem_context.h | 9 +++++++++ drivers/gpu/drm/i915/intel_lrc.c | 12 +++++++++++- 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 0bcbe32..d040858 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -388,6 +388,10 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, trace_i915_context_create(ctx); atomic_set(&ctx->req_cnt, 0); + ctx->slice_cnt = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask); + ctx->subslice_cnt = hweight8( + INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); + ctx->eu_cnt = INTEL_INFO(dev_priv)->sseu.eu_per_subslice; return ctx; } diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index e824b15..e000530 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -199,6 +199,15 @@ struct i915_gem_context { * go for low/medium/high load configuration of the GPU. */ atomic_t req_cnt; + + /** slice_cnt: used to set the # of slices to be enabled. */ + u8 slice_cnt; + + /** subslice_cnt: used to set the # of subslices to be enabled. */ + u8 subslice_cnt; + + /** eu_cnt: used to set the # of eu to be enabled. */ + u8 eu_cnt; }; static inline bool i915_gem_context_is_closed(const struct i915_gem_context *ctx) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d33f5ac..a17f676 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -171,6 +171,7 @@ static void execlists_init_reg_state(u32 *reg_state, struct i915_gem_context *ctx, struct intel_engine_cs *engine, struct intel_ring *ring); +static u32 make_rpcs(struct drm_i915_private *dev_priv); static inline struct i915_priolist *to_priolist(struct rb_node *rb) { @@ -417,12 +418,21 @@ execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) static u64 execlists_update_context(struct i915_request *rq) { + u32 rpcs_config = 0; struct intel_context *ce = rq->hw_context; + u32 *reg_state = ce->lrc_reg_state; + struct i915_gem_context *ctx = rq->gem_context; struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt; - u32 *reg_state = ce->lrc_reg_state; reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); + /* FIXME: To avoid stale rpcs config, move it to context_pin */ + if (ctx->pid && ctx->name && (rq->engine->id == RCS)) { + rpcs_config = make_rpcs(ctx->i915); + reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); + CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, + rpcs_config); + } /* True 32b PPGTT with dynamic page allocation: update PDP * registers and point the unallocated PDPs to scratch page.