From patchwork Tue Mar 19 08:44:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10859055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE4BC1669 for ; Tue, 19 Mar 2019 08:19:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C78132942D for ; Tue, 19 Mar 2019 08:19:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BC0F1295C6; Tue, 19 Mar 2019 08:19:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6BF3A2942D for ; Tue, 19 Mar 2019 08:19:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DBE7C89A61; Tue, 19 Mar 2019 08:19:42 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5005B89A44 for ; Tue, 19 Mar 2019 08:19:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Mar 2019 01:19:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,497,1544515200"; d="scan'208";a="153013695" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.74.134]) by fmsmga002.fm.intel.com with ESMTP; 19 Mar 2019 01:19:36 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Mar 2019 14:14:18 +0530 Message-Id: <1552985064-11974-11-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552985064-11974-1-git-send-email-uma.shankar@intel.com> References: <1552985064-11974-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [v6 10/16] drm/i915/icl: Add ICL Plane Degamma Register definition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add register definitions for ICL Plane Degamma. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0beed42..b9a2084 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10181,6 +10181,48 @@ enum skl_power_gate { #define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \ _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe)) +/* Plane Color Register for Gen11+ */ +/* Plane Degamma Registers */ +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x70100 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x71100 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x70200 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x71200 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B) +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B) + +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe),\ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_INDEX_4_A 0x70400 +#define _PLANE_PRE_CSC_GAMC_INDEX_4_B 0x71400 +#define _PLANE_PRE_CSC_GAMC_INDEX_5_A 0x70500 +#define _PLANE_PRE_CSC_GAMC_INDEX_5_B 0x71500 +#define _PLANE_PRE_CSC_GAMC_INDEX_4(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_4_A, _PLANE_PRE_CSC_GAMC_INDEX_4_B) +#define _PLANE_PRE_CSC_GAMC_INDEX_5(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_5_A, _PLANE_PRE_CSC_GAMC_INDEX_5_B) + +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_4(pipe),\ + _PLANE_PRE_CSC_GAMC_INDEX_5(pipe)) + +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701D4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711D4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702D4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712D4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B) +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B) + +#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe),\ + _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_DATA_4_A 0x704D4 +#define _PLANE_PRE_CSC_GAMC_DATA_4_B 0x714D4 +#define _PLANE_PRE_CSC_GAMC_DATA_5_A 0x705D4 +#define _PLANE_PRE_CSC_GAMC_DATA_5_B 0x715D4 +#define _PLANE_PRE_CSC_GAMC_DATA_4(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_4_A, _PLANE_PRE_CSC_GAMC_DATA_4_B) +#define _PLANE_PRE_CSC_GAMC_DATA_5(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_5_A, _PLANE_PRE_CSC_GAMC_DATA_5_B) + +#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_4(pipe),\ + _PLANE_PRE_CSC_GAMC_DATA_5(pipe)) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)