From patchwork Fri Mar 29 13:32:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaolin Zhang X-Patchwork-Id: 10876349 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 111D5139A for ; Fri, 29 Mar 2019 04:01:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EFBBA2905F for ; Fri, 29 Mar 2019 04:00:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E2AC129065; Fri, 29 Mar 2019 04:00:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=2.0 tests=BAYES_00,DATE_IN_FUTURE_06_12, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7838B2905F for ; Fri, 29 Mar 2019 04:00:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E587C6E815; Fri, 29 Mar 2019 04:00:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id EFFBB6E815; Fri, 29 Mar 2019 04:00:57 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Mar 2019 21:00:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,283,1549958400"; d="scan'208";a="129648453" Received: from vca-bj120.bj.intel.com ([10.240.192.119]) by orsmga008.jf.intel.com with ESMTP; 28 Mar 2019 21:00:55 -0700 From: Xiaolin Zhang To: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 09:32:38 -0400 Message-Id: <1553866364-111114-3-git-send-email-xiaolin.zhang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1553866364-111114-1-git-send-email-xiaolin.zhang@intel.com> References: <1553866364-111114-1-git-send-email-xiaolin.zhang@intel.com> Subject: [Intel-gfx] [PATCH v4 2/8] drm/i915: vgpu shared memory setup for pv optimization X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhenyu.z.wang@intel.com, hang.yuan@intel.com, zhiyuan.lv@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To enable vgpu pv features, we need to setup a shared memory page which will be used for data exchange directly accessed between both guest and backend i915 driver to avoid emulation trap cost. guest i915 will allocate this page memory and then pass it's physical address to backend i915 driver through PVINFO register so that backend i915 driver can access this shared page meory without any trap cost with the help form hyperviser's read guest gpa functionality. guest i915 will send VGT_G2V_SHARED_PAGE_SETUP notification to host GVT once shared memory setup finished. the layout of the shared_page also defined as well in this patch which is used for pv features implementation. v0: RFC v1: addressed RFC comment to move both shared_page_lock and shared_page to i915_virtual_gpu structure v2: packed i915_virtual_gpu structure v3: added SHARED_PAGE_SETUP g2v notification for pv shared_page setup v4: added intel_vgpu_setup_shared_page() in i915_vgpu_pv.c Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_drv.h | 4 +++- drivers/gpu/drm/i915/i915_pvinfo.h | 5 ++++- drivers/gpu/drm/i915/i915_vgpu.c | 38 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_vgpu.h | 17 +++++++++++++++++ 4 files changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b0c50bb..6abd112 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1248,7 +1248,9 @@ struct i915_virtual_gpu { bool active; u32 caps; u32 pv_caps; -}; + spinlock_t shared_page_lock; + struct gvt_shared_page *shared_page; +} __packed; /* used in computing the new watermarks state */ struct intel_wm_config { diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h index 619305a..4657bf7 100644 --- a/drivers/gpu/drm/i915/i915_pvinfo.h +++ b/drivers/gpu/drm/i915/i915_pvinfo.h @@ -46,6 +46,7 @@ enum vgt_g2v_type { VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY, VGT_G2V_EXECLIST_CONTEXT_CREATE, VGT_G2V_EXECLIST_CONTEXT_DESTROY, + VGT_G2V_SHARED_PAGE_SETUP, VGT_G2V_MAX, }; @@ -110,7 +111,9 @@ struct vgt_if { u32 pv_caps; - u32 rsv7[0x200 - 25]; /* pad to one page */ + u64 shared_page_gpa; + + u32 rsv7[0x200 - 27]; /* pad to one page */ } __packed; #define vgtif_reg(x) \ diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index e9f6d96..1530552 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -135,6 +135,9 @@ void intel_vgt_deballoon(struct drm_i915_private *dev_priv) for (i = 0; i < 4; i++) vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]); + + if (dev_priv->vgpu.shared_page) + free_page((unsigned long)dev_priv->vgpu.shared_page); } static int vgt_balloon_space(struct i915_ggtt *ggtt, @@ -286,6 +289,36 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) * i915 vgpu PV support for Linux */ +/* + * shared_page setup for VGPU PV features + */ +static int intel_vgpu_setup_shared_page(struct drm_i915_private *dev_priv) +{ + struct intel_uncore *uncore = &dev_priv->uncore; + u64 gpa; + + dev_priv->vgpu.shared_page = (struct gvt_shared_page *) + get_zeroed_page(GFP_KERNEL); + if (!dev_priv->vgpu.shared_page) { + DRM_ERROR("out of memory for shared page memory\n"); + return -ENOMEM; + } + + /* pass guest memory pa address to GVT and then read back to verify */ + gpa = __pa(dev_priv->vgpu.shared_page); + __raw_i915_write64(uncore, vgtif_reg(shared_page_gpa), gpa); + if (gpa != __raw_i915_read64(uncore, vgtif_reg(shared_page_gpa))) { + DRM_ERROR("vgpu: passed shared_page_gpa failed\n"); + free_page((unsigned long)dev_priv->vgpu.shared_page); + return -EIO; + } + __raw_i915_write32(uncore, vgtif_reg(g2v_notify), + VGT_G2V_SHARED_PAGE_SETUP); + spin_lock_init(&dev_priv->vgpu.shared_page_lock); + + return 0; +} + /** * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities * @dev_priv: i915 device private @@ -313,6 +346,11 @@ bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv) if (!pvcaps) return false; + if (intel_vgpu_setup_shared_page(dev_priv)) { + dev_priv->vgpu.pv_caps = 0; + return false; + } + __raw_i915_write32(uncore, vgtif_reg(pv_caps), pvcaps); return true; diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h index 91010fc..68127d4 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.h +++ b/drivers/gpu/drm/i915/i915_vgpu.h @@ -26,6 +26,23 @@ #include "i915_pvinfo.h" +/* + * A shared page(4KB) between gvt and VM, could be allocated by guest driver + * or a fixed location in PCI bar 0 region + */ +struct pv_ppgtt_update { + u64 pdp; + u64 start; + u64 length; + u32 cache_level; +}; + +struct gvt_shared_page { + struct pv_ppgtt_update pv_ppgtt; + u32 ring_id; + u64 descs[EXECLIST_MAX_PORTS]; +}; + void i915_check_vgpu(struct drm_i915_private *dev_priv); bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);