From patchwork Fri Mar 29 13:32:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaolin Zhang X-Patchwork-Id: 10876351 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94E011708 for ; Fri, 29 Mar 2019 04:01:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C15E2905F for ; Fri, 29 Mar 2019 04:01:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6D3E029065; Fri, 29 Mar 2019 04:01:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=2.0 tests=BAYES_00,DATE_IN_FUTURE_06_12, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BCBD92905F for ; Fri, 29 Mar 2019 04:01:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DCC096E816; Fri, 29 Mar 2019 04:01:06 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1722C6E818; Fri, 29 Mar 2019 04:01:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Mar 2019 21:01:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,283,1549958400"; d="scan'208";a="129648491" Received: from vca-bj120.bj.intel.com ([10.240.192.119]) by orsmga008.jf.intel.com with ESMTP; 28 Mar 2019 21:01:02 -0700 From: Xiaolin Zhang To: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 09:32:39 -0400 Message-Id: <1553866364-111114-4-git-send-email-xiaolin.zhang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1553866364-111114-1-git-send-email-xiaolin.zhang@intel.com> References: <1553866364-111114-1-git-send-email-xiaolin.zhang@intel.com> Subject: [Intel-gfx] [PATCH v4 3/8] drm/i915: vgpu ppgtt update pv optimization X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhenyu.z.wang@intel.com, hang.yuan@intel.com, zhiyuan.lv@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch extends vgpu ppgtt g2v notification to notify host GVT-g of ppgtt update from guest including alloc_4lvl, clear_4lv4 and insert_4lvl. These updates use the shared memory page to pass struct pv_ppgtt_update from guest to GVT which is used for pv optimiation implemeation within host GVT side. This patch also add one new pv_caps level to control ppgtt update. Use PV_PPGTT_UPDATE to control this level of pv optimization. v0: RFC v1: rebased v2: added pv callbacks for vm.{allocate_va_range, insert_entries, clear_range} within ppgtt. v3: rebased, disable huge page ppgtt support when using PVMMIO ppgtt update due to complex and performance impact. v4: moved alloc/insert/clear_4lvl pv callbacks into i915_vgpu_pv.c and added a single intel_vgpu_config_pv_caps() for vgpu pv callbacks setup. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_gem.c | 3 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 8 ++++ drivers/gpu/drm/i915/i915_pvinfo.h | 3 ++ drivers/gpu/drm/i915/i915_vgpu.c | 84 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_vgpu.h | 17 ++++++++ 6 files changed, 120 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f6cdd5f..c96a6d0 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4826,7 +4826,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv) int ret; /* We need to fallback to 4K pages if host doesn't support huge gtt. */ - if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv)) + if ((intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv)) + || intel_vgpu_enabled_pv_caps(dev_priv, PV_PPGTT_UPDATE)) mkwrite_device_info(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 736c845..8011527 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -923,7 +923,7 @@ static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4, * This is the top-level structure in 4-level page tables used on gen8+. * Empty entries are always scratch pml4e. */ -static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm, +void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm, u64 start, u64 length) { struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); @@ -1162,7 +1162,7 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, } while (iter->sg); } -static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, +void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags) @@ -1444,7 +1444,7 @@ static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm, &i915_vm_to_ppgtt(vm)->pdp, start, length); } -static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, +int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, u64 start, u64 length) { struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); @@ -1571,6 +1571,9 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915) ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl; ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl; ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl; + + if (intel_vgpu_active(i915)) + intel_vgpu_config_pv_caps(i915, PV_PPGTT_UPDATE, ppgtt); } else { err = __pdp_init(&ppgtt->vm, &ppgtt->pdp); if (err) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 83ded9f..03cff75 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -625,6 +625,14 @@ int gen6_ppgtt_pin(struct i915_hw_ppgtt *base); void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base); void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base); +void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm, + u64 start, u64 length); +void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, u32 flags); +int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm, + u64 start, u64 length); + void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h index 4657bf7..2408a9d 100644 --- a/drivers/gpu/drm/i915/i915_pvinfo.h +++ b/drivers/gpu/drm/i915/i915_pvinfo.h @@ -47,6 +47,9 @@ enum vgt_g2v_type { VGT_G2V_EXECLIST_CONTEXT_CREATE, VGT_G2V_EXECLIST_CONTEXT_DESTROY, VGT_G2V_SHARED_PAGE_SETUP, + VGT_G2V_PPGTT_L4_ALLOC, + VGT_G2V_PPGTT_L4_CLEAR, + VGT_G2V_PPGTT_L4_INSERT, VGT_G2V_MAX, }; diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index 1530552..87a0ca5 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -80,6 +80,9 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv) dev_priv->vgpu.active = true; + /* guest driver PV capability */ + dev_priv->vgpu.pv_caps = PV_PPGTT_UPDATE; + if (!intel_vgpu_check_pv_caps(dev_priv)) { DRM_INFO("Virtual GPU for Intel GVT-g detected.\n"); return; @@ -289,6 +292,68 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) * i915 vgpu PV support for Linux */ +static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm, + u64 start, u64 length) +{ + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct i915_pml4 *pml4 = &ppgtt->pml4; + struct drm_i915_private *dev_priv = vm->i915; + struct pv_ppgtt_update *pv_ppgtt = + &dev_priv->vgpu.shared_page->pv_ppgtt; + u64 orig_start = start; + u64 orig_length = length; + + gen8_ppgtt_clear_4lvl(vm, start, length); + + pv_ppgtt->pdp = px_dma(pml4); + pv_ppgtt->start = orig_start; + pv_ppgtt->length = orig_length; + I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR); +} + +static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm, + struct i915_vma *vma, + enum i915_cache_level cache_level, + u32 flags) +{ + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct drm_i915_private *dev_priv = vm->i915; + struct pv_ppgtt_update *pv_ppgtt = + &dev_priv->vgpu.shared_page->pv_ppgtt; + + gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags); + + pv_ppgtt->pdp = px_dma(&ppgtt->pml4); + pv_ppgtt->start = vma->node.start; + pv_ppgtt->length = vma->node.size; + pv_ppgtt->cache_level = cache_level; + I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT); +} + +static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm, + u64 start, u64 length) +{ + struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct i915_pml4 *pml4 = &ppgtt->pml4; + struct drm_i915_private *dev_priv = vm->i915; + struct pv_ppgtt_update *pv_ppgtt = + &dev_priv->vgpu.shared_page->pv_ppgtt; + int ret; + u64 orig_start = start; + u64 orig_length = length; + + ret = gen8_ppgtt_alloc_4lvl(vm, start, length); + if (ret) + return ret; + + pv_ppgtt->pdp = px_dma(pml4); + pv_ppgtt->start = orig_start; + pv_ppgtt->length = orig_length; + I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC); + + return 0; +} + /* * shared_page setup for VGPU PV features */ @@ -319,6 +384,25 @@ static int intel_vgpu_setup_shared_page(struct drm_i915_private *dev_priv) return 0; } +/* + * config guest driver PV ops for different PV features + */ +void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv, + enum pv_caps cap, void *data) +{ + struct i915_hw_ppgtt *ppgtt; + + if (!intel_vgpu_enabled_pv_caps(dev_priv, cap)) + return; + + if (cap == PV_PPGTT_UPDATE) { + ppgtt = (struct i915_hw_ppgtt *)data; + ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl_pv; + ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl_pv; + ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl_pv; + } +} + /** * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities * @dev_priv: i915 device private diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h index 68127d4..dfe2eb4 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.h +++ b/drivers/gpu/drm/i915/i915_vgpu.h @@ -27,6 +27,13 @@ #include "i915_pvinfo.h" /* + * define different capabilities of PV optimization + */ +enum pv_caps { + PV_PPGTT_UPDATE = 0x1, +}; + +/* * A shared page(4KB) between gvt and VM, could be allocated by guest driver * or a fixed location in PCI bar 0 region */ @@ -65,9 +72,19 @@ intel_vgpu_has_pv_caps(struct drm_i915_private *dev_priv) return dev_priv->vgpu.caps & VGT_CAPS_PV; } +static inline bool +intel_vgpu_enabled_pv_caps(struct drm_i915_private *dev_priv, + enum pv_caps cap) +{ + return intel_vgpu_active(dev_priv) && intel_vgpu_has_pv_caps(dev_priv) + && (dev_priv->vgpu.pv_caps & cap); +} + int intel_vgt_balloon(struct drm_i915_private *dev_priv); void intel_vgt_deballoon(struct drm_i915_private *dev_priv); /* i915 vgpu pv related functions */ bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv); +void intel_vgpu_config_pv_caps(struct drm_i915_private *dev_priv, + enum pv_caps cap, void *data); #endif /* _I915_VGPU_H_ */