From patchwork Wed Apr 3 04:30:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kirankumar X-Patchwork-Id: 10882829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A95E71708 for ; Wed, 3 Apr 2019 04:38:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8AAFD289A2 for ; Wed, 3 Apr 2019 04:38:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7ED72289CE; Wed, 3 Apr 2019 04:38:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 24BB7289BF for ; Wed, 3 Apr 2019 04:38:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD0476E4A2; Wed, 3 Apr 2019 04:38:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 91F6A6E4A2 for ; Wed, 3 Apr 2019 04:38:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Apr 2019 21:38:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,303,1549958400"; d="scan'208";a="128176120" Received: from kskumar.iind.intel.com ([10.66.247.75]) by orsmga007.jf.intel.com with ESMTP; 02 Apr 2019 21:38:07 -0700 From: kiran.s.kumar@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 3 Apr 2019 10:00:25 +0530 Message-Id: <1554265825-31346-1-git-send-email-kiran.s.kumar@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH] drm/i915: FBC needs vblank before enable / disable. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Kiran Kumar S As per the display workaround #1200, FBC needs wait for vblank before enabling and before disabling FBC. In some cases, depending on whether FBC was compressing in that frame, several control signals in the compression engine also will fail to properly recognize the final segment of the frame as a result of the missing last pixel indication. As a result of this, we're seeing corrupted cache line/compression indicators after FBC re-enables which causes underruns or corruption when they're used to decompress. WA sequence as below: 1) Display enables plane 1A 2) Wait for 1 vblank 3) FBC gets enabled 4) Wait for 1 VBLANK 5) Turn off FBC In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen got corrupted. With the above WA, issue was resolved. Change-Id: I2465610bb0a82df99e5c53b1eb4ed74565996b1e Signed-off-by: Kiran Kumar S --- drivers/gpu/drm/i915/intel_display.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8576a7f799f2..5118a36782eb 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13207,8 +13207,11 @@ static void intel_update_crtc(struct drm_crtc *crtc, if (pipe_config->update_pipe && !pipe_config->enable_fbc) intel_fbc_disable(intel_crtc); - else if (new_plane_state) + else if (new_plane_state) { + /* Display WA #1200: GLK */ + intel_wait_for_vblank(dev_priv, intel_crtc->pipe); intel_fbc_enable(intel_crtc, pipe_config, new_plane_state); + } intel_begin_crtc_commit(crtc, old_crtc_state); @@ -13419,6 +13422,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) dev_priv->display.crtc_disable(old_intel_crtc_state, state); intel_crtc->active = false; + /* Display WA #1200: GLK */ + intel_wait_for_vblank(dev_priv, intel_crtc->pipe); intel_fbc_disable(intel_crtc); intel_disable_shared_dpll(old_intel_crtc_state);