From patchwork Mon Apr 29 03:10:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaolin Zhang X-Patchwork-Id: 10921109 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 62C3E912 for ; Mon, 29 Apr 2019 03:11:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5214528739 for ; Mon, 29 Apr 2019 03:11:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 464252873D; Mon, 29 Apr 2019 03:11:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DDF3428739 for ; Mon, 29 Apr 2019 03:11:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D51F8916B; Mon, 29 Apr 2019 03:11:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id DEAC989160; Mon, 29 Apr 2019 03:11:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Apr 2019 20:11:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,408,1549958400"; d="scan'208";a="146648277" Received: from xzhan34-mobl3.bj.intel.com ([10.238.154.121]) by fmsmga007.fm.intel.com with ESMTP; 28 Apr 2019 20:11:50 -0700 From: Xiaolin Zhang To: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Mon, 29 Apr 2019 11:10:58 +0800 Message-Id: <1556507458-24684-9-git-send-email-xiaolin.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556507458-24684-1-git-send-email-xiaolin.zhang@intel.com> References: <1556507458-24684-1-git-send-email-xiaolin.zhang@intel.com> Subject: [Intel-gfx] [PATCH v5 8/8] drm/i915/gvt: GVTg support context submission pv optimization X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhenyu.z.wang@intel.com, hang.yuan@intel.com, zhiyuan.lv@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP implemented context submission pv optimizaiton within GVTg. GVTg to read context submission data (elsp_data) from the shared_page directly without trap cost and eliminate execlist HW behavior emulation without injecting context switch interrupt to guest under PV submisison mechanism. v0: RFC v1: rebase v2: rebase v3: report pv context submission cap and handle VGT_G2V_ELSP_SUBMIT g2v pv notification. v4: eliminate execlist HW emulation and don't inject context switch interrupt to guest under PV submisison mechanism. v5: rebase Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/gvt/execlist.c | 6 ++++++ drivers/gpu/drm/i915/gvt/handlers.c | 12 ++++++++++++ drivers/gpu/drm/i915/gvt/vgpu.c | 1 + 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index f21b8fb..e52bfd6 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -382,6 +382,9 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload) int ring_id = workload->ring_id; int ret; + if (VGPU_PVCAP(vgpu, PV_SUBMISSION)) + return 0; + if (!workload->emulate_schedule_in) return 0; @@ -429,6 +432,9 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload) goto out; } + if (VGPU_PVCAP(vgpu, PV_SUBMISSION)) + goto out; + ret = emulate_execlist_ctx_schedule_out(execlist, &workload->ctx_desc); out: intel_vgpu_unpin_mm(workload->shadow_mm); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 4648d17..1e5f109 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1712,6 +1712,18 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, return -EINVAL; execlist = &vgpu->submission.execlist[ring_id]; + if (VGPU_PVCAP(vgpu, PV_SUBMISSION) && VGT_G2V_PV_SUBMISSION == data) { + struct pv_submission pv_elsp[I915_NUM_ENGINES]; + u32 pv_elsp_off = offsetof(struct gvt_shared_page, pv_elsp); + + if (intel_gvt_read_shared_page(vgpu, pv_elsp_off, &pv_elsp, + I915_NUM_ENGINES * sizeof(struct pv_submission))) + return ret; + + memcpy(&execlist->elsp_dwords.data, pv_elsp[ring_id].descs, + 8 * EXECLIST_MAX_PORTS); + return intel_vgpu_submit_execlist(vgpu, ring_id); + } execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; if (execlist->elsp_dwords.index == 3) { diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index dd89c12..47dd29e 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -51,6 +51,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) if (!intel_vtd_active()) vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) = PV_PPGTT_UPDATE; + vgpu_vreg_t(vgpu, vgtif_reg(pv_caps)) |= PV_SUBMISSION; vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = vgpu_aperture_gmadr_base(vgpu);