From patchwork Tue May 14 09:43:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Swati2" X-Patchwork-Id: 10942599 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B048092A for ; Tue, 14 May 2019 09:47:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E7DF285A1 for ; Tue, 14 May 2019 09:47:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9308E285FF; Tue, 14 May 2019 09:47:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 117CE285A1 for ; Tue, 14 May 2019 09:47:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 710DB8926E; Tue, 14 May 2019 09:47:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 71F8689276 for ; Tue, 14 May 2019 09:47:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 May 2019 02:47:38 -0700 X-ExtLoop1: 1 Received: from genxfsim-shark-bay-client-platform.iind.intel.com ([10.223.74.155]) by orsmga008.jf.intel.com with ESMTP; 14 May 2019 02:47:36 -0700 From: Swati Sharma To: intel-gfx@lists.freedesktop.org Date: Tue, 14 May 2019 15:13:21 +0530 Message-Id: <1557827010-24239-4-git-send-email-swati2.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1557827010-24239-1-git-send-email-swati2.sharma@intel.com> References: <1557827010-24239-1-git-send-email-swati2.sharma@intel.com> Subject: [Intel-gfx] [v6][PATCH 03/12] drm/i915: Add intel_color_lut_equal() to compare hw and sw gamma/degamma lut values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP v3: -Rebase v4: -Renamed intel_compare_color_lut() to intel_color_lut_equal() [Jani] -Added the default label above the correct label [Jani] -Corrected smatch warn "variable dereferenced before check" [Dan Carpenter] v5: -Added condition (!blob1 && !blob2) return true [Jani] -Called PIPE_CONF_CHECK_COLOR_LUT inside if (!adjust) [Jani] -Added #undef PIPE_CONF_CHECK_COLOR_LUT [Jani] v6: -Added func intel_color_get_bit_precision() to get bit precision for gamma and degamma lut readout depending upon platform and corresponding to load_luts() [Ankit] -Added debug log for color para in intel_dump_pipe_config [Jani] -Made patch11 as patch3 [Jani] I could think of adding intel_color_get_bit_precision() to be the way to get away with bit precision problem for degamma and gamma (its like a table having hard coded values depening on gamma_mode). If anybody could think of better way then this then please guide. Signed-off-by: Swati Sharma --- drivers/gpu/drm/i915/intel_color.c | 93 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color.h | 7 +++ drivers/gpu/drm/i915/intel_display.c | 24 ++++++++++ 3 files changed, 124 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 50b98ee..1e60369 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -1251,6 +1251,99 @@ static int icl_color_check(struct intel_crtc_state *crtc_state) return 0; } +void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + if (HAS_GMCH(dev_priv)) { + if (IS_CHERRYVIEW(dev_priv)) { + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { + *bp_gamma = 8; + return; + } + if (crtc_state->cgm_mode == CGM_PIPE_MODE_GAMMA) + *bp_gamma = 10; + } else if (INTEL_GEN(dev_priv) >= 4) { + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + *bp_gamma = 8; + else + *bp_gamma = 16; + } else { + *bp_gamma = 8; + } + } else { + if (INTEL_GEN(dev_priv) >= 11) { + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) == + GAMMA_MODE_MODE_8BIT) + *bp_gamma = 8; + else + *bp_gamma = 10; + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + *bp_gamma = 8; + else + *bp_gamma = 10; + } else if (INTEL_GEN(dev_priv) >= 7) { + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + *bp_gamma = 8; + else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) + *bp_gamma = 10; + else + *bp_gamma = 10; + } else { + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) + *bp_gamma = 8; + else + *bp_gamma = 10; + } + } +} + +static inline bool err_check(struct drm_color_lut *sw_lut, + struct drm_color_lut *hw_lut, u32 err) +{ + return ((abs((long)hw_lut->red - sw_lut->red)) <= err) && + ((abs((long)hw_lut->blue - sw_lut->blue)) <= err) && + ((abs((long)hw_lut->green - sw_lut->green)) <= err); +} + +bool intel_color_lut_equal(struct drm_property_blob *blob1, + struct drm_property_blob *blob2, + u32 bit_precision) +{ + struct drm_color_lut *sw_lut, *hw_lut; + int sw_lut_size, hw_lut_size, i; + u32 err; + + if (!blob1 && !blob2) + return true; + + if (!blob1) + return true; + + if (!blob2) + return false; + + sw_lut_size = drm_color_lut_size(blob1); + hw_lut_size = drm_color_lut_size(blob2); + + if (sw_lut_size != hw_lut_size) + return false; + + sw_lut = blob1->data; + hw_lut = blob2->data; + + err = 0xffff >> bit_precision; + + for (i = 0; i < sw_lut_size; i++) { + if (!err_check(&hw_lut[i], &sw_lut[i], err)) + return false; + } + + return true; +} + void intel_color_init(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); diff --git a/drivers/gpu/drm/i915/intel_color.h b/drivers/gpu/drm/i915/intel_color.h index 057e8ac..f2872d3 100644 --- a/drivers/gpu/drm/i915/intel_color.h +++ b/drivers/gpu/drm/i915/intel_color.h @@ -6,13 +6,20 @@ #ifndef __INTEL_COLOR_H__ #define __INTEL_COLOR_H__ +#include + struct intel_crtc_state; struct intel_crtc; +struct drm_property_blob; void intel_color_init(struct intel_crtc *crtc); int intel_color_check(struct intel_crtc_state *crtc_state); void intel_color_commit(const struct intel_crtc_state *crtc_state); void intel_color_load_luts(const struct intel_crtc_state *crtc_state); void intel_color_get_config(struct intel_crtc_state *crtc_state); +bool intel_color_lut_equal(struct drm_property_blob *blob1, + struct drm_property_blob *blob2, + u32 bit_precision); +void intel_color_get_bit_precision(struct intel_crtc_state *crtc_state, int *bp_gamma); #endif /* __INTEL_COLOR_H__ */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3e01028..46985c15 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11570,6 +11570,16 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, drm_rect_width(&state->base.dst), drm_rect_height(&state->base.dst)); } + + if (IS_CHERRYVIEW(dev_priv)) + DRM_DEBUG_KMS("cgm_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n", + pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config->gamma_enable, + pipe_config->csc_enable); + else + DRM_DEBUG_KMS("csc_mode:%d gamma_mode:%d gamma_enable:%d csc_enable:%d\n", + pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config->gamma_enable, + pipe_config->csc_enable); + } static bool check_digital_port_conflicts(struct drm_atomic_state *state) @@ -11947,6 +11957,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv) bool adjust) { bool ret = true; + u32 bp_gamma = 0; bool fixup_inherited = adjust && (current_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED) && !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED); @@ -12098,6 +12109,15 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv) } \ } while (0) +#define PIPE_CONF_CHECK_COLOR_LUT(name, bit_precision) do { \ + if (!intel_color_lut_equal(current_config->name, \ + pipe_config->name, bit_precision)) { \ + pipe_config_err(adjust, __stringify(name), \ + "hw_state doesn't match sw_state\n"); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_QUIRK(quirk) \ ((current_config->quirks | pipe_config->quirks) & (quirk)) @@ -12193,6 +12213,9 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv) PIPE_CONF_CHECK_X(csc_mode); PIPE_CONF_CHECK_BOOL(gamma_enable); PIPE_CONF_CHECK_BOOL(csc_enable); + + intel_color_get_bit_precision(pipe_config, &bp_gamma); + PIPE_CONF_CHECK_COLOR_LUT(base.gamma_lut, bp_gamma); } PIPE_CONF_CHECK_BOOL(double_wide); @@ -12255,6 +12278,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv) #undef PIPE_CONF_CHECK_FLAGS #undef PIPE_CONF_CHECK_CLOCK_FUZZY #undef PIPE_CONF_QUIRK +#undef PIPE_CONF_CHECK_COLOR_LUT return ret; }