| Message ID | 1559123462-7343-3-git-send-email-swati2.sharma@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: adding state checker for gamma lut values | expand |
On Wed, 29 May 2019, Swati Sharma <swati2.sharma@intel.com> wrote: > In this patch, intel_color_get_config() is enabled and support > for read_luts() will be added platform by platform incrementally > in the follow-up patches. > > v4: -Renamed intel_get_color_config to intel_color_get_config [Jani] > -Added the user early on such that support for get_color_config() > can be added platform by platform incrementally [Jani] > v5: -Incorrect place for calling intel_color_get_config() in > haswell_get_pipe_config() [Ville] > v6: -Renamed intel_color_read_luts() to intel_color_get_config() > [Jani and Ville] > > Signed-off-by: Swati Sharma <swati2.sharma@intel.com> I pushed patches 1 and 2, thanks for the patches. BR, Jani. > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 05177f3..3e01028 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -8351,6 +8351,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe)); > > i9xx_get_pipe_color_config(pipe_config); > + intel_color_get_config(pipe_config); > > if (INTEL_GEN(dev_priv) < 4) > pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; > @@ -9426,6 +9427,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, > pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); > > i9xx_get_pipe_color_config(pipe_config); > + intel_color_get_config(pipe_config); > > if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { > struct intel_shared_dpll *pll; > @@ -9874,6 +9876,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > i9xx_get_pipe_color_config(pipe_config); > } > > + intel_color_get_config(pipe_config); > + > power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); > WARN_ON(power_domain_mask & BIT_ULL(power_domain));
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 05177f3..3e01028 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8351,6 +8351,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe)); i9xx_get_pipe_color_config(pipe_config); + intel_color_get_config(pipe_config); if (INTEL_GEN(dev_priv) < 4) pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; @@ -9426,6 +9427,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); i9xx_get_pipe_color_config(pipe_config); + intel_color_get_config(pipe_config); if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { struct intel_shared_dpll *pll; @@ -9874,6 +9876,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, i9xx_get_pipe_color_config(pipe_config); } + intel_color_get_config(pipe_config); + power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); WARN_ON(power_domain_mask & BIT_ULL(power_domain));
In this patch, intel_color_get_config() is enabled and support for read_luts() will be added platform by platform incrementally in the follow-up patches. v4: -Renamed intel_get_color_config to intel_color_get_config [Jani] -Added the user early on such that support for get_color_config() can be added platform by platform incrementally [Jani] v5: -Incorrect place for calling intel_color_get_config() in haswell_get_pipe_config() [Ville] v6: -Renamed intel_color_read_luts() to intel_color_get_config() [Jani and Ville] Signed-off-by: Swati Sharma <swati2.sharma@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 4 ++++ 1 file changed, 4 insertions(+)