From patchwork Tue Jul 23 11:31:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaolin Zhang X-Patchwork-Id: 11053723 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA8DC6C5 for ; Tue, 23 Jul 2019 02:57:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B95D6285BD for ; Tue, 23 Jul 2019 02:57:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ACFDF285C8; Tue, 23 Jul 2019 02:57:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=2.0 tests=BAYES_00,DATE_IN_FUTURE_06_12, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3D01B285BD for ; Tue, 23 Jul 2019 02:57:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A1CEE89E2A; Tue, 23 Jul 2019 02:57:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6272289E2A; Tue, 23 Jul 2019 02:57:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jul 2019 19:57:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,297,1559545200"; d="scan'208";a="171040375" Received: from vca-bj102.bj.intel.com ([10.240.193.76]) by fmsmga007.fm.intel.com with ESMTP; 22 Jul 2019 19:57:07 -0700 From: Xiaolin Zhang To: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Tue, 23 Jul 2019 19:31:56 +0800 Message-Id: <1563881524-147440-2-git-send-email-xiaolin.zhang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1563881524-147440-1-git-send-email-xiaolin.zhang@intel.com> References: <1563881524-147440-1-git-send-email-xiaolin.zhang@intel.com> Subject: [Intel-gfx] [PATCH v8 1/9] drm/i915: introduced vgpu pv capability X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhenyu.z.wang@intel.com, hang.yuan@intel.com, zhiyuan.lv@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP pv capability for vgpu was introduced by pv_caps in struct i915_virtual_gpu and a new pv_caps register for host GVT was defined in struct vgt_if for vgpu pv optimization. both of them are used to control different feature pv optimization supported and implemented by both guest and host. These fields are default zero, no any pv feature enabled. it also adds VGT_CAPS_PV capability BIT for guest to check GVTg can support PV feature or not. v0: RFC, introudced enable_pvmmio module parameter. v1: addressed RFC comment to remove enable_pvmmio module parameter by pv capability check. v2: rebase. v3: distinct pv caps from guest and host. renamed enable_pvmmio to pvmmio_caps which is used for host pv caps. v4: consolidated all pv related functons into a single file i915_vgpu.c and renamed pvmmio to pv_caps. v5: rebase. v6: rebase. v7: rebase. Signed-off-by: Xiaolin Zhang --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pvinfo.h | 5 ++++- drivers/gpu/drm/i915/i915_vgpu.c | 44 +++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_vgpu.h | 9 ++++++++ 4 files changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0e44cc4..fa5dc47 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -93,6 +93,7 @@ #include "i915_vma.h" #include "intel_gvt.h" +#include "i915_pvinfo.h" /* General customization: */ @@ -1078,6 +1079,7 @@ struct i915_frontbuffer_tracking { struct i915_virtual_gpu { bool active; u32 caps; + u32 pv_caps; }; /* used in computing the new watermarks state */ diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h index 683e97a..ad398b4 100644 --- a/drivers/gpu/drm/i915/i915_pvinfo.h +++ b/drivers/gpu/drm/i915/i915_pvinfo.h @@ -57,6 +57,7 @@ enum vgt_g2v_type { #define VGT_CAPS_FULL_PPGTT BIT(2) #define VGT_CAPS_HWSP_EMULATION BIT(3) #define VGT_CAPS_HUGE_GTT BIT(4) +#define VGT_CAPS_PV BIT(5) struct vgt_if { u64 magic; /* VGT_MAGIC */ @@ -109,7 +110,9 @@ struct vgt_if { u32 execlist_context_descriptor_lo; u32 execlist_context_descriptor_hi; - u32 rsv7[0x200 - 24]; /* pad to one page */ + u32 pv_caps; + + u32 rsv7[0x200 - 25]; /* pad to one page */ } __packed; #define vgtif_offset(x) (offsetof(struct vgt_if, x)) diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index dbd1fa3..9b37dd1 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -95,7 +95,14 @@ void i915_detect_vgpu(struct drm_i915_private *dev_priv) dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps)); dev_priv->vgpu.active = true; - DRM_INFO("Virtual GPU for Intel GVT-g detected.\n"); + + if (!intel_vgpu_check_pv_caps(dev_priv, shared_area)) { + DRM_INFO("Virtual GPU for Intel GVT-g detected.\n"); + return; + } + + DRM_INFO("Virtual GPU for Intel GVT-g detected with pv_caps 0x%x.\n", + dev_priv->vgpu.pv_caps); out: pci_iounmap(pdev, shared_area); @@ -297,3 +304,38 @@ int intel_vgt_balloon(struct i915_ggtt *ggtt) DRM_ERROR("VGT balloon fail\n"); return ret; } + +/* + * i915 vgpu PV support for Linux + */ + +/** + * intel_vgpu_check_pv_caps - detect virtual GPU PV capabilities + * @dev_priv: i915 device private + * + * This function is called at the initialization stage, to detect VGPU + * PV capabilities + * + * If guest wants to enable pv_caps, it needs to config it explicitly + * through vgt_if interface from gvt layer. + */ +bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv, + void __iomem *shared_area) +{ + u32 gvt_pvcaps; + u32 pvcaps = 0; + + if (!intel_vgpu_has_pv_caps(dev_priv)) + return false; + + /* PV capability negotiation between PV guest and GVT */ + gvt_pvcaps = readl(shared_area + vgtif_offset(pv_caps)); + pvcaps = dev_priv->vgpu.pv_caps & gvt_pvcaps; + dev_priv->vgpu.pv_caps = pvcaps; + writel(pvcaps, shared_area + vgtif_offset(pv_caps)); + + if (!pvcaps) + return false; + + return true; +} diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h index 8b3663d..bbe56b5 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.h +++ b/drivers/gpu/drm/i915/i915_vgpu.h @@ -43,7 +43,16 @@ return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT; } +static inline bool +intel_vgpu_has_pv_caps(struct drm_i915_private *dev_priv) +{ + return dev_priv->vgpu.caps & VGT_CAPS_PV; +} + int intel_vgt_balloon(struct i915_ggtt *ggtt); void intel_vgt_deballoon(struct i915_ggtt *ggtt); +/* i915 vgpu pv related functions */ +bool intel_vgpu_check_pv_caps(struct drm_i915_private *dev_priv, + void __iomem *shared_area); #endif /* _I915_VGPU_H_ */