| Message ID | 158c7b30e56d22aa3f9c9e51e87b9d89687d74d5.1726681620.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/pps: hide VLV/CHV PPS pipe stuff inside intel_pps.c | expand |
On Wed, Sep 18, 2024 at 08:47:43PM +0300, Jani Nikula wrote: > While the struct intel_pps vlv_pps_pipe and vlv_active_pipe members are > only relevant for VLV/CHV, we still initialize them on all platforms and > check them on BXT/GLK. Wrap all access inside VLV/CHV checks for > consistency. > > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 6 +++--- > drivers/gpu/drm/i915/display/intel_pps.c | 11 ++++++----- > 2 files changed, 9 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 9dd86523012f..9f908dbd45ea 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -6867,8 +6867,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, > return false; > > intel_dp->reset_link_params = true; > - intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; > - intel_dp->pps.vlv_active_pipe = INVALID_PIPE; > > /* Preserve the current hw state. */ > intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); > @@ -6895,8 +6893,10 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, > intel_dp_set_default_sink_rates(intel_dp); > intel_dp_set_default_max_sink_lane_count(intel_dp); > > - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > + intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; > intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp); > + } > > intel_dp_aux_init(intel_dp); > intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c > index 2d8d911988ab..649dc6ad2278 100644 > --- a/drivers/gpu/drm/i915/display/intel_pps.c > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > @@ -472,16 +472,17 @@ void intel_pps_reset_all(struct intel_display *display) > for_each_intel_dp(display->drm, encoder) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > - drm_WARN_ON(display->drm, > - intel_dp->pps.vlv_active_pipe != INVALID_PIPE); > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + drm_WARN_ON(display->drm, > + intel_dp->pps.vlv_active_pipe != INVALID_PIPE); Might make sense to just split this whole function into vlv/chv vs. bxt/glk versions. It's called from platform specific code only so each caller knows which one it wants. Series is Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > if (encoder->type != INTEL_OUTPUT_EDP) > continue; > > - if (DISPLAY_VER(display) >= 9) > - intel_dp->pps.bxt_pps_reset = true; > - else > + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; > + else > + intel_dp->pps.bxt_pps_reset = true; > } > } > > -- > 2.39.2
On Wed, 18 Sep 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote: > On Wed, Sep 18, 2024 at 08:47:43PM +0300, Jani Nikula wrote: >> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c >> index 2d8d911988ab..649dc6ad2278 100644 >> --- a/drivers/gpu/drm/i915/display/intel_pps.c >> +++ b/drivers/gpu/drm/i915/display/intel_pps.c >> @@ -472,16 +472,17 @@ void intel_pps_reset_all(struct intel_display *display) >> for_each_intel_dp(display->drm, encoder) { >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder); >> >> - drm_WARN_ON(display->drm, >> - intel_dp->pps.vlv_active_pipe != INVALID_PIPE); >> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) >> + drm_WARN_ON(display->drm, >> + intel_dp->pps.vlv_active_pipe != INVALID_PIPE); > > Might make sense to just split this whole function > into vlv/chv vs. bxt/glk versions. It's called from > platform specific code only so each caller knows > which one it wants. Agreed. Patch on the list [1]. > Series is > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Many thanks, pushed to din. BR, Jani. [1] https://lore.kernel.org/r/20240919090427.1859032-1-jani.nikula@intel.com
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9dd86523012f..9f908dbd45ea 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6867,8 +6867,6 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, return false; intel_dp->reset_link_params = true; - intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; - intel_dp->pps.vlv_active_pipe = INVALID_PIPE; /* Preserve the current hw state. */ intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); @@ -6895,8 +6893,10 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, intel_dp_set_default_sink_rates(intel_dp); intel_dp_set_default_max_sink_lane_count(intel_dp); - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp); + } intel_dp_aux_init(intel_dp); intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 2d8d911988ab..649dc6ad2278 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -472,16 +472,17 @@ void intel_pps_reset_all(struct intel_display *display) for_each_intel_dp(display->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - drm_WARN_ON(display->drm, - intel_dp->pps.vlv_active_pipe != INVALID_PIPE); + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + drm_WARN_ON(display->drm, + intel_dp->pps.vlv_active_pipe != INVALID_PIPE); if (encoder->type != INTEL_OUTPUT_EDP) continue; - if (DISPLAY_VER(display) >= 9) - intel_dp->pps.bxt_pps_reset = true; - else + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) intel_dp->pps.vlv_pps_pipe = INVALID_PIPE; + else + intel_dp->pps.bxt_pps_reset = true; } }
While the struct intel_pps vlv_pps_pipe and vlv_active_pipe members are only relevant for VLV/CHV, we still initialize them on all platforms and check them on BXT/GLK. Wrap all access inside VLV/CHV checks for consistency. Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 6 +++--- drivers/gpu/drm/i915/display/intel_pps.c | 11 ++++++----- 2 files changed, 9 insertions(+), 8 deletions(-)