From patchwork Fri Sep 4 04:21:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Srinivas X-Patchwork-Id: 11755779 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 622C3138C for ; Fri, 4 Sep 2020 04:26:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4AE0620748 for ; Fri, 4 Sep 2020 04:26:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4AE0620748 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE9B06EA6C; Fri, 4 Sep 2020 04:26:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 530CD6E9FD; Fri, 4 Sep 2020 04:26:43 +0000 (UTC) IronPort-SDR: FgURxwfxzMAgtDWN3QJ8wl05D8EBKMhlSKY839b7gmMRbdiZmPa4l1CSb01Z6/EtbX8X7TCzrc hJDF+WeWJBLw== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="137744349" X-IronPort-AV: E=Sophos;i="5.76,388,1592895600"; d="scan'208";a="137744349" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2020 21:26:43 -0700 IronPort-SDR: +7HlVh2r0ivBnlIvbVpN0BP0uVqpTcT7ijsdZ5fCW/lzU6DuYwmIC1j5i42y6f7Ga/HVm72PJ7 PFA9j2yn1hDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,388,1592895600"; d="scan'208";a="315714440" Received: from vsrini4-xps-8920.iind.intel.com (HELO localhost.localdomain) ([10.223.163.28]) by orsmga002.jf.intel.com with ESMTP; 03 Sep 2020 21:26:41 -0700 From: Vidya Srinivas To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 4 Sep 2020 09:51:30 +0530 Message-Id: <1599193291-2705-2-git-send-email-vidya.srinivas@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599193291-2705-1-git-send-email-vidya.srinivas@intel.com> References: <1599193291-2705-1-git-send-email-vidya.srinivas@intel.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915/dp: TPS4 PHY test pattern compliance support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Khaled Almahallawy Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. v2: uniform bit names TP4a/b/c (Manasi) Signed-off-by: Khaled Almahallawy Reviewed-by: Manasi Navare Tested-by: Khaled Almahallawy --- drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 04231ca5643b..a8a3ffcef5dc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5403,7 +5403,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) &intel_dp->compliance.test_data.phytest; struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); enum pipe pipe = crtc->pipe; - u32 pattern_val; + u32 pattern_val, dp_tp_ctl; switch (data->phy_pattern) { case DP_PHY_TEST_PATTERN_NONE: @@ -5443,7 +5443,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_PHY_TEST_PATTERN_CP2520_PAT1: /* * FIXME: Ideally pattern should come from DPCD 0x24A. As * current firmware of DPR-100 could not set it, so hardcoding @@ -5455,6 +5455,16 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; + case DP_PHY_TEST_PATTERN_CP2520_PAT3: + DRM_DEBUG_KMS("Set TPS4 Phy Test Pattern\n"); + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + dp_tp_ctl = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); + dp_tp_ctl &= ~DP_TP_CTL_TRAIN_PAT4_SEL_MASK; + dp_tp_ctl |= DP_TP_CTL_TRAIN_PAT4_SEL_TP4a; + dp_tp_ctl &= ~DP_TP_CTL_LINK_TRAIN_MASK; + dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT4; + intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl); + break; default: WARN(1, "Invalid Phy Test Pattern\n"); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ab4b1abd4364..4850890918dc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9974,6 +9974,10 @@ enum skl_power_gate { #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)