| Message ID | 1945e70fb2d39c690644f2ec0d9c3d4a4e032cb6.1709733981.git.jani.nikula@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mst: enable MST mode for 128b/132b single-stream sideband | expand |
On Wed, Mar 06, 2024 at 04:07:17PM +0200, Jani Nikula wrote: > If the sink supports 128b/132b and single-stream sideband messaging, > enable MST mode. > > With this, the topology manager will still write DP_MSTM_CTRL, which > should be ignored by the sink. In the future, the topology manager > should probably only set the sideband messaging related parts of the > register. > > Cc: Arun R Murthy <arun.r.murthy@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 3956604d8b00..4787dc15797a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4069,7 +4069,8 @@ intel_dp_mst_mode_choose(struct intel_dp *intel_dp, > if (!intel_dp_mst_source_support(intel_dp)) > return DRM_DP_SST; > > - if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG) > + if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && > + !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) > return DRM_DP_SST; The one question that comes to mind is whether we actually want to use SST+sideband? I don't think there can be sinks that only support SST+sideband but don't support SST+no-sideband can there? The benefits from using the no-sideband path would be: - Use optimal link configuration instead of the max. I suppose we could make intel_dp_mst.c do this as well, at least for the SST+sideband. - Port sync is not supported by intel_dp_mst.c currently. Though I think current hw should be capable of port sync even in full MST mode, just need to implement it. - intel_dp_mst.c is currently limited to 8bpc. We should just remove that restriction now that Imre's bandwidth stuff should be able to cope with link bw limits properly. OK, so all those benefits are more or less artificial at this point, and we could work towards fixing them, even for MST proper. Anyways, we can revisit this later if we decide that no-sideband is the better choice for whatever reason. Series is: Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > return sink_mst_mode; > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3956604d8b00..4787dc15797a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4069,7 +4069,8 @@ intel_dp_mst_mode_choose(struct intel_dp *intel_dp, if (!intel_dp_mst_source_support(intel_dp)) return DRM_DP_SST; - if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG) + if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG && + !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B)) return DRM_DP_SST; return sink_mst_mode;
If the sink supports 128b/132b and single-stream sideband messaging, enable MST mode. With this, the topology manager will still write DP_MSTM_CTRL, which should be ignored by the sink. In the future, the topology manager should probably only set the sideband messaging related parts of the register. Cc: Arun R Murthy <arun.r.murthy@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)