From patchwork Wed Jan 27 11:01:11 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Li Peng X-Patchwork-Id: 75384 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o0R31cdV014833 for ; Wed, 27 Jan 2010 03:01:39 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DFA2C9E8D2; Tue, 26 Jan 2010 19:01:37 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C0229E880 for ; Tue, 26 Jan 2010 19:01:35 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 26 Jan 2010 19:01:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.49,350,1262592000"; d="scan'208";a="487328058" Received: from unknown (HELO pli1.bj.intel.com) ([172.16.180.154]) by orsmga002.jf.intel.com with ESMTP; 26 Jan 2010 19:01:02 -0800 Date: Wed, 27 Jan 2010 19:01:11 +0800 From: Li Peng To: Eric Anholt Message-ID: <20100127110111.GA3266@pli1.bj.intel.com> References: <20100119133257.GA2038@pli1.bj.intel.com> <87ocki3yov.fsf@pollan.anholt.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87ocki3yov.fsf@pollan.anholt.net> User-Agent: Mutt/1.5.20 (2009-08-17) Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH resend] drm/i915: enable memory self refresh on 9xx X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 847006c..3921e5a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -306,11 +306,14 @@ #define I915_ERROR_MEMORY_REFRESH (1<<1) #define I915_ERROR_INSTRUCTION (1<<0) #define INSTPM 0x020c0 +#define INSTPM_SELF_EN (1<<12) /* 915GM only */ #define ACTHD 0x020c8 #define FW_BLC 0x020d8 #define FW_BLC2 0x020dc #define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define FW_BLC_SELF_EN (1<<15) +#define FW_BLC_SELF_EN_MASK (1<<31) +#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ +#define FW_BLC_SELF_EN (1<<15) /* 945 only */ #define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 #define LM_BURST_LENGTH 0x00000700 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 45da78e..d042955 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2629,7 +2629,13 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, srwm = total_size - sr_entries; if (srwm < 0) srwm = 1; - I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); + if (IS_I945G(dev) || IS_I945GM(dev)) + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); + else if (IS_I915GM(dev)) { + /* 915M has a smaller SRWM field */ + I915_WRITE(FW_BLC_SELF, srwm & 0x3f); + I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); + } } DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", @@ -3879,6 +3885,11 @@ static void intel_idle_update(struct work_struct *work) mutex_lock(&dev->struct_mutex); + if (IS_I945G(dev) || IS_I945GM(dev)) { + DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); + } + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { /* Skip inactive CRTCs */ if (!crtc->fb) @@ -3912,6 +3923,15 @@ void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj) if (!drm_core_check_feature(dev, DRIVER_MODESET)) return; + if (IS_I945G(dev) || IS_I945GM(dev)) { + u32 fw_blc_self; + + DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); + fw_blc_self = I915_READ(FW_BLC_SELF); + fw_blc_self &= ~FW_BLC_SELF_EN; + I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); + } + if (!dev_priv->busy) dev_priv->busy = true; else