From patchwork Tue Jun 29 03:04:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Wang X-Patchwork-Id: 108482 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o5T34Mg8007491 for ; Tue, 29 Jun 2010 03:04:58 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8693E9E960 for ; Mon, 28 Jun 2010 20:04:22 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C9EC9E710 for ; Mon, 28 Jun 2010 20:04:11 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 28 Jun 2010 20:04:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.53,501,1272870000"; d="asc'?c'?scan'208";a="294092594" Received: from zhen-devel.sh.intel.com (HELO zhen-devel) ([10.239.13.159]) by azsmga001.ch.intel.com with ESMTP; 28 Jun 2010 20:04:09 -0700 Date: Tue, 29 Jun 2010 11:04:09 +0800 From: Zhenyu Wang To: intel-gfx Message-ID: <20100629030409.GG10521@zhen-devel.sh.intel.com> Mail-Followup-To: intel-gfx MIME-Version: 1.0 User-Agent: Mutt/1.5.20 (2009-06-14) Subject: [Intel-gfx] implement 'wait' instruction X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list Reply-To: Zhenyu Wang List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Mime-version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 29 Jun 2010 03:04:58 +0000 (UTC) diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index a6fcd83..3a01000 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -520,6 +520,20 @@ static INLINE struct brw_reg brw_acc_reg( void ) 0); } +static INLINE struct brw_reg brw_notification_1_reg(void) +{ + + return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, + BRW_ARF_NOTIFICATION_COUNT, + 1, + BRW_REGISTER_TYPE_UD, + BRW_VERTICAL_STRIDE_0, + BRW_WIDTH_1, + BRW_HORIZONTAL_STRIDE_0, + BRW_SWIZZLE_XXXX, + WRITEMASK_X); +} + static INLINE struct brw_reg brw_flag_reg( void ) { @@ -919,6 +933,8 @@ void brw_land_fwd_jump(struct brw_compile *p, void brw_NOP(struct brw_compile *p); +void brw_WAIT(struct brw_compile *p); + /* Special case: there is never a destination, execution size will be * taken from src0: */ diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 34dfe10..10e9ebc 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -906,6 +906,20 @@ void brw_CMP(struct brw_compile *p, } } +/* Issue 'wait' instruction for n1, host could program MMIO + to wake up thread. */ +void brw_WAIT (struct brw_compile *p) +{ + struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WAIT); + struct brw_reg src = brw_notification_1_reg(); + + brw_set_dest(insn, src); + brw_set_src0(insn, src); + brw_set_src1(insn, brw_null_reg()); + insn->header.execution_size = 0; /* must */ + insn->header.predicate_control = 0; + insn->header.compression_control = 0; +} /***********************************************************************