diff mbox

drm/i915: fix FDI frequency check

Message ID 20100707140643.35f516d2@virtuousgeek.org
State Deferred, archived
Headers show

Commit Message

Jesse Barnes July 7, 2010, 9:06 p.m. UTC
None

Comments

Eric Anholt July 8, 2010, 6:21 p.m. UTC | #1
On Wed, 7 Jul 2010 14:06:43 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Since mode->clock is in kHz we should be checking against 2700000
> instead of just 27000.  This patch gets my x201s working again (well
> working as well as it ever was anyway).
> 
> When looking for this I also noticed we set link_bw to 270000, but the
> calculation is different.  Does it also need to use kHz or we using
> 10kHz internally?
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Worked for me.  I've put a squash of the bad patch into this one in that
place in the history.
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c6bcc2f..dfbdf88 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -322,6 +322,9 @@  struct intel_limit {
 #define IRONLAKE_DP_P1_MIN		1
 #define IRONLAKE_DP_P1_MAX		2
 
+/* FDI */
+#define IRONLAKE_FDI_FREQ		2700000 /* in kHz for mode->clock */
+
 static bool
 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 		    int target, int refclk, intel_clock_t *best_clock);
@@ -2410,7 +2413,7 @@  static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 	struct drm_device *dev = crtc->dev;
 	if (HAS_PCH_SPLIT(dev)) {
 		/* FDI link clock is fixed at 2.7G */
-		if (mode->clock * 3 > 27000 * 4)
+		if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
 			return false;
 	}