From patchwork Tue Dec 21 23:11:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 425311 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBLNBMMj021433 for ; Tue, 21 Dec 2010 23:11:51 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 410C59EF60 for ; Tue, 21 Dec 2010 15:11:22 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy2-pub.bluehost.com (oproxy2-pub.bluehost.com [67.222.39.60]) by gabe.freedesktop.org (Postfix) with SMTP id 33DE89EEF6 for ; Tue, 21 Dec 2010 15:11:02 -0800 (PST) Received: (qmail 18285 invoked by uid 0); 21 Dec 2010 23:11:01 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by oproxy2.bluehost.com with SMTP; 21 Dec 2010 23:11:01 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=virtuousgeek.org; h=Received:Date:From:To:Subject:Message-ID:X-Mailer:Mime-Version:Content-Type:Content-Transfer-Encoding:X-Identified-User; b=m8EAwWxYn4ypbhW23CMR+kn0GUg1fDGxJJlf9dG98kR2Fw/6gLN4LFZj2EMKvym9AfAb4XcvdyEq99jdHXaLFDxL2CAIQ+9gLYbKmhEzSioQk7XQTZ7HwcRBIcAOL64v; Received: from c-67-174-193-198.hsd1.ca.comcast.net ([67.174.193.198] helo=jbarnes-desktop) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.69) (envelope-from ) id 1PVBMD-0003gN-HS for intel-gfx@lists.freedesktop.org; Tue, 21 Dec 2010 16:11:01 -0700 Date: Tue, 21 Dec 2010 15:11:00 -0800 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Message-ID: <20101221151100.6d1dc1e9@jbarnes-desktop> X-Mailer: Claws Mail 3.7.6 (GTK+ 2.18.9; x86_64-redhat-linux-gnu) Mime-Version: 1.0 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.174.193.198 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH] drm/i915: enable rc6 support on Ironlake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 21 Dec 2010 23:11:51 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d60860e..7f93a13 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -145,6 +145,8 @@ #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) +#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) +#define MI_SUSPEND_FLUSH_EN (1<<0) #define MI_REPORT_HEAD MI_INSTR(0x07, 0) #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) #define MI_OVERLAY_CONTINUE (0x0<<21) @@ -1131,8 +1133,12 @@ #define RCUPEI 0x111b0 #define RCDNEI 0x111b4 #define MCHBAR_RENDER_STANDBY 0x111b8 +#define RS1_ENABLE (1<<31) +#define RS2_ENABLE (1<<30) +#define RS3_ENABLE (1<<29) #define RCX_SW_EXIT (1<<23) #define RSX_STATUS_MASK 0x00700000 +#define RC_CSTATE_RS2 (3<<4) #define VIDCTL 0x111c0 #define VIDSTS 0x111c8 #define VIDSTART 0x111cc /* 8 bits */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8806596..eae18ed 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6368,17 +6368,30 @@ void intel_enable_clock_gating(struct drm_device *dev) I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); } + if ((IS_GEN4(dev) || IS_GEN5(dev)) && IS_MOBILE(dev)) { + if (dev_priv->pwrctx == NULL) + dev_priv->pwrctx = intel_alloc_context_page(dev); + if (dev_priv->pwrctx) { + struct drm_i915_gem_object *obj = dev_priv->pwrctx; + I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN); + I915_WRITE(MCHBAR_RENDER_STANDBY, + (I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT) | RS1_ENABLE | RS2_ENABLE | RC_CSTATE_RS2); + } + } + /* * GPU can automatically power down the render unit if given a page * to save state. */ - if (IS_IRONLAKE_M(dev) && 0) { /* XXX causes a failure during suspend */ + if (IS_IRONLAKE_M(dev)) { if (dev_priv->renderctx == NULL) dev_priv->renderctx = intel_alloc_context_page(dev); if (dev_priv->renderctx) { struct drm_i915_gem_object *obj = dev_priv->renderctx; - if (BEGIN_LP_RING(4) == 0) { + if (BEGIN_LP_RING(6) == 0) { + OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); OUT_RING(MI_SET_CONTEXT); + OUT_RING(MI_SUSPEND_FLUSH); OUT_RING(obj->gtt_offset | MI_MM_SPACE_GTT | MI_SAVE_EXT_STATE_EN | @@ -6393,16 +6406,6 @@ void intel_enable_clock_gating(struct drm_device *dev) "Disable RC6\n"); } - if (IS_GEN4(dev) && IS_MOBILE(dev)) { - if (dev_priv->pwrctx == NULL) - dev_priv->pwrctx = intel_alloc_context_page(dev); - if (dev_priv->pwrctx) { - struct drm_i915_gem_object *obj = dev_priv->pwrctx; - I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN); - I915_WRITE(MCHBAR_RENDER_STANDBY, - I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); - } - } } void intel_disable_clock_gating(struct drm_device *dev)