@@ -1275,7 +1275,6 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
int i;
uint8_t voltage;
- bool clock_recovery = false;
int tries;
u32 reg;
uint32_t DP = intel_dp->DP;
@@ -1298,7 +1297,6 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
memset(intel_dp->train_set, 0, 4);
voltage = 0xff;
tries = 0;
- clock_recovery = false;
for (;;) {
/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
uint32_t signal_levels;
@@ -1324,10 +1322,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
if (!intel_dp_get_link_status(intel_dp))
break;
- if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
- clock_recovery = true;
+ if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count))
break;
- }
/* Check to see if we've tried the max voltage */
for (i = 0; i < intel_dp->lane_count; i++)
@@ -1357,7 +1353,6 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
struct drm_device *dev = intel_dp->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- bool channel_eq = false;
int tries, cr_tries;
u32 reg;
uint32_t DP = intel_dp->DP;
@@ -1365,7 +1360,6 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
/* channel equalization */
tries = 0;
cr_tries = 0;
- channel_eq = false;
for (;;) {
/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
uint32_t signal_levels;
@@ -1405,10 +1399,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
continue;
}
- if (intel_channel_eq_ok(intel_dp)) {
- channel_eq = true;
+ if (intel_channel_eq_ok(intel_dp))
break;
- }
/* Try 5 times, then try clock recovery if that fails */
if (tries > 5) {
Leftover from the training split, we don't need these guys anymore. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>