From patchwork Fri Aug 12 22:18:09 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 1062132 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7CMJ8ag027197 for ; Fri, 12 Aug 2011 22:19:28 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E2AB69EFED for ; Fri, 12 Aug 2011 15:19:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy4-pub.bluehost.com (oproxy4-pub.bluehost.com [69.89.21.11]) by gabe.freedesktop.org (Postfix) with SMTP id 578219EDD5 for ; Fri, 12 Aug 2011 15:18:24 -0700 (PDT) Received: (qmail 10359 invoked by uid 0); 12 Aug 2011 22:18:23 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy1.bluehost.com with SMTP; 12 Aug 2011 22:18:23 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Content-Transfer-Encoding:Content-Type:Mime-Version:References:In-Reply-To:Message-ID:Subject:To:From:Date; bh=OlogKTlca3Vsq+qJYkSkWT/Z9DrO0KZ8CvK1LcoaQgI=; b=qiJbzKq/e3St5ztAWsByCk+Hoz6/ywEHUCvigQpOiyJf7exqwz77LWLH7FsHhYm6yKOfMyxsH+VLVIGh8kDUpseceFpWCL0o4PSFuMZrx3ziepYUPzva6a7Y4GscB6AA; Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189] helo=jbarnes-desktop) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.76) (envelope-from ) id 1Qs03b-0000ts-Kw for intel-gfx@lists.freedesktop.org; Fri, 12 Aug 2011 16:18:23 -0600 Date: Fri, 12 Aug 2011 15:18:09 -0700 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Message-ID: <20110812151809.7fdab276@jbarnes-desktop> In-Reply-To: <1313186133-2724-1-git-send-email-jbarnes@virtuousgeek.org> References: <1313186133-2724-1-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: Claws Mail 3.7.6 (GTK+ 2.22.0; x86_64-pc-linux-gnu) Mime-Version: 1.0 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 12 Aug 2011 22:19:28 +0000 (UTC) On Fri, 12 Aug 2011 14:55:32 -0700 Jesse Barnes wrote: > GFX_MODE controls important behavior like PPGTT, run lists, and TLB > invalidate behavior. On the SDV I'm using, the TLB invalidation mode > was defaulting to "pipe control only" which meant regular MI_FLUSHes > wouldn't actually flush the TLB, leading to all sorts of stale data > getting used. > > So initialize it to 0 at ring buffer init time until we actually use > PIPE_CONTROL for TLB invalidation. Ignore this one, see below for an updated patch that uses bit definitions and makes sure the register gets reset at GPU reset time as well. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7033e01..26641ad 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -375,6 +375,7 @@ # define MI_FLUSH_ENABLE (1 << 11) #define GFX_MODE 0x02520 +#define GFX_MODE_GEN7 0x0229c #define GFX_RUN_LIST_ENABLE (1<<15) #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) #define GFX_SURFACE_FAULT_ENABLE (1<<12) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 47b9b27..6dad947 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -290,6 +290,9 @@ static int init_render_ring(struct intel_ring_buffer *ring) if (IS_GEN6(dev) || IS_GEN7(dev)) mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; I915_WRITE(MI_MODE, mode); + if (IS_GEN7(dev)) + I915_WRITE(GFX_MODE_GEN7, (GFX_REPLAY_MODE << 16) | + GFX_REPLAY_MODE); } if (INTEL_INFO(dev)->gen >= 6) {