From patchwork Fri Aug 12 22:28:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 1062142 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7CMT77s006743 for ; Fri, 12 Aug 2011 22:29:29 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C3419EB6B for ; Fri, 12 Aug 2011 15:29:07 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id B12989E774 for ; Fri, 12 Aug 2011 15:28:47 -0700 (PDT) Received: (qmail 29027 invoked by uid 0); 12 Aug 2011 22:28:47 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy3.bluehost.com with SMTP; 12 Aug 2011 22:28:47 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Content-Transfer-Encoding:Content-Type:Mime-Version:References:In-Reply-To:Message-ID:Subject:Cc:From:Date; bh=kvGU+II35s2YZ0NG4zblD4G1OC6V410WYDKpuIo5EW4=; b=jTVy9hgOM1YKI0Qm9Pcdixq0nmXvgrgC+XgSnU3BKlSrQcJslkH9JsYySkyyckmcyR3vmdDiqBwatacZyG9f9PVCCR3d7VW0YIizc7DJoHoqYtOVE8q/OemjFxVyBrNv; Received: from c-67-161-37-189.hsd1.ca.comcast.net ([67.161.37.189] helo=jbarnes-desktop) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.76) (envelope-from ) id 1Qs0Df-00011a-6j for intel-gfx@lists.freedesktop.org; Fri, 12 Aug 2011 16:28:47 -0600 Date: Fri, 12 Aug 2011 15:28:32 -0700 From: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org Message-ID: <20110812152832.6c922a17@jbarnes-desktop> In-Reply-To: <20110812151809.7fdab276@jbarnes-desktop> References: <1313186133-2724-1-git-send-email-jbarnes@virtuousgeek.org> <20110812151809.7fdab276@jbarnes-desktop> X-Mailer: Claws Mail 3.7.6 (GTK+ 2.22.0; x86_64-pc-linux-gnu) Mime-Version: 1.0 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 12 Aug 2011 22:29:29 +0000 (UTC) On Fri, 12 Aug 2011 15:18:09 -0700 Jesse Barnes wrote: > On Fri, 12 Aug 2011 14:55:32 -0700 > Jesse Barnes wrote: > > > GFX_MODE controls important behavior like PPGTT, run lists, and TLB > > invalidate behavior. On the SDV I'm using, the TLB invalidation mode > > was defaulting to "pipe control only" which meant regular MI_FLUSHes > > wouldn't actually flush the TLB, leading to all sorts of stale data > > getting used. > > > > So initialize it to 0 at ring buffer init time until we actually use > > PIPE_CONTROL for TLB invalidation. > > Ignore this one, see below for an updated patch that uses bit > definitions and makes sure the register gets reset at GPU reset time as > well. Ignore the last one too. Third time's the charm! Tested-by: Kenneth Graunke diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7033e01..26641ad 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -375,6 +375,7 @@ # define MI_FLUSH_ENABLE (1 << 11) #define GFX_MODE 0x02520 +#define GFX_MODE_GEN7 0x0229c #define GFX_RUN_LIST_ENABLE (1<<15) #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) #define GFX_SURFACE_FAULT_ENABLE (1<<12) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 47b9b27..0b17036 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -290,6 +290,10 @@ static int init_render_ring(struct intel_ring_buffer *ring) if (IS_GEN6(dev) || IS_GEN7(dev)) mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; I915_WRITE(MI_MODE, mode); + if (IS_GEN7(dev)) + I915_WRITE(GFX_MODE_GEN7, ((GFX_TLB_INVALIDATE_ALWAYS | + GFX_REPLAY_MODE) << 16) | + GFX_REPLAY_MODE); } if (INTEL_INFO(dev)->gen >= 6) {